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for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max1385/MAX1386 set and control bias conditions for dual rf ldmos power devices found in cellular base stations. each device includes a high-side cur- rent-sense amplifier with programmable gains of 2, 10, and 25 to monitor ldmos drain current over the 20ma to 5a range. two external diode-connected transistors monitor ldmos temperatures while an internal temper- ature sensor measures the local die temperature of the max1385/MAX1386. a 12-bit adc converts the pro- grammable-gain amplifier (pga) outputs, external/inter- nal temperature readings, and two auxiliary inputs. the two gate-drive channels, each consisting of 8-bit coarse and 10-bit fine dacs and a gate-drive amplifier, generate a positive gate voltage to bias the ldmos devices. the max1385 includes a gate-drive amplifier with a gain of 2 and the MAX1386 gate-drive amplifier provides a gain of 4. the 8-bit coarse and 10-bit fine dacs allow up to 18 bits of resolution. the max1385/ MAX1386 include autocalibration features to minimize error over time, temperature, and supply voltage. the max1385/MAX1386 feature an i 2 c/spi-compatible serial interface. both devices operate from a 4.75v to 5.25v analog supply (3.2ma supply current), a 2.7v to 5.25v digital supply (3.1ma supply current), and a 4.75v to 11.0v gate-drive supply (4.5ma supply current). the max1385/MAX1386 are available in a 48-pin thin qfn package. applications rf ldmos bias control in cellular base stations industrial process control features ? integrated high-side drain current-sense pga with gain of 2, 10, or 25 ? ?.5% accuracy for sense voltage between 75mv and 250mv ? full-scale sense voltage of 100mv with gain of 25 ? full-scale sense voltage of 250mv with gain of 10 ? common-mode range of 5v to 30v drain voltage for ldmos ? adjustable low noise 0 to 5v, 0 to 10v output gate-bias voltage ranges with ?0ma gate drive ? fast clamp to 0v for ldmos protection ? 8-bit dac control of gate-bias voltage ? 10-bit dac control of gate-bias offset with temperature ? internal die temperature measurement ? external temperature measurement by diode- connected transistor (2n3904) ? internal 12-bit adc measurement of temperature, current, and voltages ? selectable i 2 c-/spi-compatible serial interface 400khz/1.7mhz/3.4mhz i 2 c-compatible control for settings and data measurement 16mhz spi-compatible control for settings and data measurement ? internal 2.5v reference ? three address inputs to control eight devices in i 2 c mode max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ________________________________________________________________ maxim integrated products 1 19-4456; rev 0; 2/09 evaluation kit available ordering information/selector guide part temp range pin-package temp error (?) v gate (v) max1385 aetm+** -40? to +85? 48 thin qfn-ep* ? 5 max1385betm+ -40? to +85? 48 thin qfn-ep* ? 5 MAX1386 aetm+** -40? to +85? 48 thin qfn-ep* ? 10 MAX1386betm+** -40? to +85? 48 thin qfn-ep* ? 10 spi is a trademark of motorola, inc. * ep = exposed pad. ** future product?ontact factory for availability. + denotes a lead(pb)-free/rohs-compliant package. pin configuration and typical operating circuit (i 2 c mode) appear at end of data sheet.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. av dd to agnd .........................................................-0.3v to +6v dv dd to dgnd.........................................................-0.3v to +6v agnd to dgnd.....................................................-0.3v to +0.3v cs1+, cs1-, cs2+, cs2- to gategnd.................-0.3v to +32v cs1- to cs1+, cs2- to cs2+ ...................................-6v to +0.3v gatev dd to gategnd .........................................-0.3v to +12v gate1, gate2 to gategnd ...........-0.3v to (gatev dd + 0.3v) safe1, safe2 to gategnd....................................-0.3v to +6v gategnd to agnd..............................................-0.3v to +0.3v all other analog inputs to agnd ............-0.3v to the lower of +6v and (av dd + 0.3v) digital inputs to dgnd ............-0.3v to the lower of +6v and (dv dd + 0.3v) sda/din, scl to dgnd...........................................-0.3v to +6v digital outputs to dgnd .........................-0.3v to (dv dd + 0.3v) maximum continuous current into any pin ........................50ma continuous power dissipation (t a = +70?) 48-pin, 7mm x 7mm, thin qfn (derate 27.8 mw/? above +70?).............................................................2222mw maximum junction temperature .....................................+150? operating temperature range ...........................-40? to +85? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v ref- dac = +2.5v, c ref = 0.1?, unless otherwise noted. t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units high-side current sense with pga common-mode input voltage range v cs+ , v cs- 530v common-mode rejection ratio cmrr 11v < v cs+ < 30v 90 db i cs+ v sense < 100mv over the common-mode range 120 195 input-bias current i cs- 0.002 ? ? pga gain = 25 0 100 pga gain = 10 0 250 full-scale sense voltage range v sense = vcs_+ - vcs_- pga gain = 2 0 1250 mv pga gain = 25 75 100 pga gain = 10 75 250 sense voltage range for accuracy of ?.5% v sense pga gain = 2 75 1250 mv pga gain = 25 20 100 pga gain = 10 20 250 sense voltage range for accuracy of ?% v sense pga gain = 2 20 1250 mv total pgaout voltage error v sense = 75mv ?.1 ?.5 % pgaout capacitive load c pgaout 100 pf pgaout settling time t hscs settles to within ?.5% of final value, r s = 50 ? , c gate = 15pf < 25 ? saturation recovery time settles to within ?.5% accuracy; from v sense = 3 x full scale < 45 ? av pga = 2 0.5 av pga = 10 2 sense-amplifier slew rate av pga = 25 2 v/?
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface _______________________________________________________________________________________ 3 electrical characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v ref- dac = +2.5v, c ref = 0.1?, unless otherwise noted. t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units av pga = 2 900 av pga = 10 720 sense-amplifier bandwidth av pga = 25 290 khz ldmos gate driver (gain = 2 and 4) i gate = ?ma 0.75 gatev dd - 0.75 output gate-drive voltage range v gate i gate = ?0ma 1 gatev dd - 1 v output impedance r gate measured at dc 0.1 ? v gate settling time t gate settles to within ?.5% of final value; r series = 50 ? , c gate = 15? 10 ms no series resistance, r series = 0 ? 010 output capacitive load (note 1) c gate r series = 50 ? 0 25,000 nf v gate noise rms noise; 1khz - 1mhz 250 nv/ hz maximum power-on transient ?00 mv output short-circuit current limit i sc 1s, sinking or sourcing ?5 ma max1385, locode = 128, hicode = 180 ? ?0 total unadjusted error no autocalibration and offset removal (note 2) tue MAX1386, locode = 128, hicode = 180 ?2 ?0 mv max1385, locode = 128, hicode = 180 ? ? total adjusted error with autocalibration and offset removal tue MAX1386, locode = 128, hicode = 180 ? ?6 mv max1385, v gate > 1v ?5 drift MAX1386, v gate > 1v ?0 ?/? clamp to zero delay 1s output safe switch on- resistance r opsw gate_ clamped to agnd (note 3) 500 ? max1385 300 amplifier bandwidth MAX1386 150 khz amplifier slew rate 0.375 v/? monitor adc dc accuracy resolution n adc 12 bits differential nonlinearity dnl adc ?.5 2 lsb integral nonlinearity inl adc (note 4) ?.6 2 lsb offset error ? ? lsb gain error (note 5) ? ? lsb gain temperature coefficient ?.4 ppm/? offset temperature coefficient ?.4 ppm/?
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 4 _______________________________________________________________________________________ electrical characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v ref- dac = +2.5v, c ref = 0.1?, unless otherwise noted. t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units channel-to-channel offset matching ?.1 lsb channel-to-channel gain matching ?.1 lsb monitor adc dynamic accuracy (1khz sine-wave input, 2.5v p-p , up to 94.4ksps) signal-to-noise plus distortion sinad 70 db total harmonic distortion thd up to the 5th harmonic -82 db spurious-free dynamic range sfdr 86 db intermodulation distortion imd f in1 = 0.99khz, f in2 = 1.02khz 76 db full-power bandwidth -3db point 10 mhz full-linear bandwidth s/(n + d) > 68db 100 khz monitor adc conversion rate external reference 0.8 power-up time t pu internal reference 70 ? conversion time t conv internally clocked 7.5 10 ? monitor adc analog input (adcin1, adcin2) input range v adcin relative to agnd (note 6) 0 v ref v input leakage current v in = 0v and v in = av dd ?.01 ? ? input capacitance c adcin 34 pf temperature measurements max1385a/MAX1386a, t a = +25? ?.25 max1385a/MAX1386a, t a = t min to t max -1.0 ?.25 +1.0 max1385b/MAX1386b, t a = +25? ?.25 internal sensor measurement error (note 1) max1385b/MAX1386b, t a = t min to t max -2.0 ?.35 +2.0 ? t a = +25? ?.4 external sensor measurement error (notes 1, 7) t a = t min to t max -3 ?.75 +3 ? temperature resolution 1/8 ?/lsb external diode drive 2.8 85 ? drive current ratio (note 8) 16.5 internal reference v refadc t a = +25? 2.494 2.500 2.506 refadc/refdac output voltage v refdac t a = +25? 2.494 2.500 2.506 v refadc/refdac output temperature coefficient tc refadc , tc refdac ?4 ppm/? refadc/refdac output impedance 6.5 k ?
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface _______________________________________________________________________________________ 5 electrical characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v ref- dac = +2.5v, c ref = 0.1?, unless otherwise noted. t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units capacitive bypass at ref 270 nf power-supply rejection ratio psrr av dd = +5v ?% 70 db external reference refadc input voltage range v refadc limited code test 1.0 av dd v v ref = 2.5v, f sample = 174ksps 60 80 refadc input current i refadc acquisition/between conversions ?.01 ? ? refdac input voltage range v refdac (note 9) 0.5 2.5 v refdac input current static current when no dac calibration 0.1 ? gate-driver coarse-dac dc accuracy resolution n cdac 8 bits integral nonlinearity inl cdac measured at gate; fine dac set at full scale ?.15 ? lsb differential nonlinearity dnl cdac guaranteed monotonic ?.05 ?.5 lsb gate-driver fine-dac dc accuracy resolution n fdac 10 bits integral nonlinearity inl fdac measured at gate; coarse dac set at full scale ?.25 ? lsb differential nonlinearity dnl fdac guaranteed monotonic ?.1 1 lsb power supplies (note 10) analog supply voltage av dd 4.75 5.25 v digital supply voltage dv dd 2.7 av dd + 0.3 v gate-drive supply voltage v gatevdd 4.75 11.00 v analog supply current i avdd av dd = 5v 3.2 4 ma digital supply current i dvdd dv dd = 2.7v to 5.25v 3.1 4.3 ma gatev dd supply current i gatevdd 3 4.5 7 ma i avdd 0.1 2 i dvdd 0.1 2 shutdown current (note 11) i pd i vddgate 0.1 2 ?
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 6 _______________________________________________________________________________________ electrical characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v ref- dac = +2.5v, c ref = 0.1?, unless otherwise noted. t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) parameter symbol conditions min typ max units v ih and v il for sda/din and scl in i 2 c operation only input high voltage v ih 0.7 x dv dd v input low voltage v il 0.3 x dv dd v input hysteresis v hys 0.1 x dv dd v v ih and v il for opsafe1 and opsafe2 input high voltage v ih 2.4 v input low voltage v il 0.4 v v ih and v il for all other digital inputs input high voltage v ih 2.2 v input low voltage v il 0.7 v v oh and v ol for a1/dout (spi), sda/din, alarm output low voltage v ol i sink = 3ma 0.4 v output high voltage v oh i source = 2ma dv dd - 0.5 v v oh and v ol for safe1, safe2, busy output low voltage v ol i sink = 0.5ma 0.4 v output high voltage v oh i source = 0.5ma dv dd - 0.5 v
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface _______________________________________________________________________________________ 7 i 2 c slow-/fast-mode timing characteristics (note 12, see figure 1) (gatev dd = +5.5v for max1385, gatev dd = +11v for MAX1386, av dd = +5v, dv dd = 2.7v to 5.25v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = -40? to +85?, unless otherwise noted). parameter symbol conditions min typ max units serial-clock frequency f scl 0 400 khz bus free time between stop and start condition t buf 1.3 ? hold time repeated start condition t hd ; sta after this period, the first clock pulse is generated 0.6 ? scl pulse-width low t low 1.3 ? scl pulse-width high t high 0.6 ? setup time repeated start condition t su;sta 0.6 ? data hold time t hd ; dat (note 13) 0 0.9 ? data setup time t su ; dat 100 ns rise time of both sda and scl signals, receiving t r (note 14) 0 300 ns fall time of both sda and scl signals, receiving t f (note 14) 0 300 ns fall time of sda signal, transmitting t f (notes 14, 15) 20 + 0.1c b 250 ns setup time for stop condition t su ; sto 0.6 ? capacitive load for each bus line c b 400 pf pulse width of spikes suppressed by the input filter t sp (note 16) 0 50 ns
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 8 _______________________________________________________________________________________ i 2 c high-speed-mode timing characteristics (note 12, see figure 2) (gatev dd = +5.5v for max1385, gatev dd = +11v for MAX1386, av dd = +5v, dv dd = 2.7v to 5.25v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = -40? to +85?, unless otherwise noted). parameter symbol conditions min typ max units serial-clock frequency f scl 0 3.4 mhz setup time repeated start condition t su;sta 160 ns hold time repeated start condition t hd;sta 160 ns scl pulse-width low t low 160 ns scl pulse-width high t high 60 ns data setup time t su;dat 10 ns data hold time t hd;dat (note 17) 0 70 ns rise time of scl signal, receiving t rcl 10 40 ns rise time of scl signal after a repeated start condition and after an acknowledge bit, receiving t rcl1 10 80 ns fall time of scl signal, receiving t fcl 10 40 ns rise time of sda signal, receiving t rda 10 80 ns fall time of sda signal, transmitting t fda 10 80 ns setup time for stop condition t su;sto 160 ns capacitive load for each bus line c b (note 18) 100 pf pulse width of spikes that are suppressed by the input filter t sp 010ns
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface _______________________________________________________________________________________ 9 note 1: guaranteed by design. note 2: total unadjusted errors are for the entire gain drive channel including the 8- and 10-bit dacs and the gate driver. they are all measured at the gate1 and gate2 outputs. offset removal refers to presetting the drain current after a room tempera- ture calibration by the user. this effectively removes the channel offset. note 3: during power-on reset, the output safe switch is closed. the output safe switch opens once both av dd and dv dd supply voltages are established. note 4: integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset err ors have been removed. note 5: offset nulled. note 6: absolute range for analog inputs is from 0 to av dd . note 7: the max1385/MAX1386 and external sensor are at the same temperature. external sensor measurement error is tested with a diode-connected 2n3904. note 8: the drive current ratio is defined as the large drive current divided by the small drive current in a temperature measure- ment. see the temperature measurements section for further details. note 9: guaranteed monotonicity. accuracy might be degraded at lower v refdac . note 10: supply current limits are valid only when digital inputs are at dv dd or dgnd. timing specifications are only guaranteed when inputs are driven rail-to-rail. note 11: shutdown supply currents are typically 0.1?. maximum specification is limited by automated test equipment. note 12: all timing specifications referred to v ih or v il levels. note 13: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of scl) to bridge the unde- fined region of scl? falling edge. note 14: c b = total capacitance of one bus line in pf; t r and t f are measured between 0.3 x dv dd and 0.7 x dv dd . note 15: for a device operating in an i 2 c-compatible system. note 16: input filters on the sda and scl inputs suppress noise spikes less than 50ns. note 17: a device must provide a data hold time to bridge the undefined part between v ih and v il of the falling edge of the scl signal. an input circuit with a threshold as low as possible for the falling edge of the scl signal minimizes this hold time. note 18: cb = total capacitance of one bus line in pf. for bus loads between 100pf and 400pf, the timing parameters should be linearly interpolated. spi timing characteristics (note 12, see figure 3) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = +5v, dv dd = 2.7v to 5.25v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = -40? to +85?, unless otherwise noted.) parameter symbol conditions min typ max units scl clock period t cp 62.5 ns scl high time t ch 25 ns scl low time t cl 25 ns din setup time t ds 10 ns din hold time t dh 0ns scl fall to dout transition t do c load = 30pf 20 ns csb fall to dout enable t dv c load = 30pf 40 ns csb rise to dout disable t tr c load = 30pf (note 12) 100 ns csb rise or fall to scl rise t css 25 ns csb pulse-width high t csw 100 ns last clock rise to csb rise t csh 50 ns
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 10 ______________________________________________________________________________________ sda scl t buf t su;sto t sp t hd;sta t su;sta t f t high t su;dat t hd;dat t low t hd;sta s s r p s t r t f t r figure 1. i 2 c slow-/fast-mode timing diagram t hd;dat sda scl t su;sto t rcl1 t rcl t high t fda sr sr t low t low t high t fcl t rda p t su;sta t hd;sta t su;dat t rcl1 figure 2. i 2 c high-speed-mode timing diagram t csh t cp t ch t css t ds scl t csw t dh csb d23 din d22 d1 d0 dout t dv t cl t do t tr t css d0 d1 figure 3. spi timing diagram
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 11 typical operating characteristics (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = +25?, unless otherwise noted.) 3.0 3.3 3.2 3.1 3.4 3.5 3.6 3.7 3.8 3.9 4.0 4.7 4.94.8 5.0 5.1 5.2 5.3 av dd supply current vs. av dd voltage max1385/86 toc01 av dd (v) i avdd (ma) av pga = 2 cmv = 12v v sense = 100mv t a = +85c t a = +25c t a = -40c dv dd supply current vs. dv dd voltage max1385/86 toc02 dv dd (v) i dvdd (ma) 5.24.74.23.73.2 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 1.00 2.7 av pga = 2 cmv = 12v v sense = 100mv t a = +25c t a = +85c t a = -40c gatev dd supply current vs. gatev dd voltage max1385/86 toc03 gatev dd (v) i gatevdd (ma) 11 10 8 9 6 7 5 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 5.0 4.0 412 av pga = 2 cmv = 12v v sense = 100mv t a = +85c t a = +25c t a = -40c total pgaout_ error vs. temperature max1385/86 toc04 temperature (c) pgaout_ error (%) 8065 35 50 -10 5 20 -25 -0.125 -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0.075 0.100 0.125 0.150 -0.150 -40 av pga = 2 cmv = 12v v sense = 100mv acquisition tracking total pgaout_ error vs. v sense max1385/86 toc05 v sense (mv) pgaout_ error (%) 1000 750 500 250 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0 0 1250 av pga = 2 cmv = 12v total pgaout_ error vs. v sense max1385/86 toc06 v sense (mv) pgaout_ error (%) 80 60 40 20 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0 0.5 -4.0 0 100 av pga = 25 cmv = 12v total pgaout_ error vs. common-mode voltage max1385/86 toc07 common-mode voltage (v) pgaout_ error (%) 3025201510 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.10 0 5 av pga = 2 v sense = 100mv pgaout_ offset voltage vs. temperature max1385/86 toc08 temperature (c) offset voltage (v) 8065 35 50 -10 5 20 -25 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 -400 -40 av pga = 2 cmv = 12v v sense = 100mv acquisition tracking v sense transient response max1385/86 toc09 100mv/div 1v/div pgaout_ v sense 10s/div
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 12 ______________________________________________________________________________________ typical operating characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = +25?, unless otherwise noted.) pgaout_ 0mv to 250mv v sense transient response max1385/86 toc10 v sense pgaout_ 10 s/div 100mv/div 1v/div pgaout_ pedestal error during calibration max1385/86 toc11 busy pgaout_ 20 s/div 2v/div 10mv/div gate_ offset compensated error vs. temperature max1385/86 toc12 temperature ( c) error voltage (mv) 80 65 -25 -10 5 35 20 50 -7 -6 -5 -4 -3 -2 -1 0 -8 -40 l_error, autocalibration h_error, autocalibration l_error, no autocalibration h_error, no autocalibration v gate vs. power-on time max1385/86 toc13 v gate_ 400 s/div 50mv/div charge current vs. v gate max1385/86 toc15 v gate_ 1ms/div i gate_ 2v/div 20ma/div gate_ settling time vs. load capacitance max1385/86 toc14 load capacitance ( f) settling time (ms) 10 1 2 4 6 8 10 12 14 16 0 0.1 100 r series = 50 ? gate_ voltage swing vs. load resistance max1385/86 toc16 load resistance ( ? ) gate_ voltage swing (v) 10,000 1000 100 1 2 3 4 5 6 7 8 9 10 0 10 100,000 glitch energy max1385/86 toc17 1 s/div 10mv/div
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 13 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0400 200 600 800 1000 integral nonlinearity vs. digital input code (10-bit fine dac) max1385/86 toc19 digital input code inl (lsb) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 differential nonlinearity vs. digital input code (8-bit dac) max1385/86 toc20 digital input code dnl (lsb) 0 100 50 150 200 250 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 differential nonlinearity vs. digital input code (10-bit fine dac) max1385/86 toc21 digital input code dnl (lsb) 0 400 200 600 800 1000 -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 2000 1000 3000 4000 integral nonlinearity vs. digital output code (adc) max1385/86 toc22 digital output code inl (lsb) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 2000 1000 3000 4000 differential nonlinearity vs. digital output code (adc) max1385/86 toc23 digital output code dnl (lsb) -160 -140 -120 -100 -80 -60 -40 -20 0 0 5 10 15 20 25 fft plot max1385/86 toc24 frequency (khz) amplitude (db) f in = 303hz f sample = 49.15khz typical operating characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = +25?, unless otherwise noted.) -1.0 -0.4 -0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 integral nonlinearity vs. digital input code (8-bit coarse dac) max1385/86 toc18 digital input code inl (lsb)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 14 ______________________________________________________________________________________ -0.05 -0.03 -0.04 -0.01 -0.02 0.01 0 0.02 0.04 0.03 0.05 -40 -10 5 20 -25 35 50 65 80 adc gain error vs. temperature max1385/86 toc28 temperature ( c) gain error (%) av dd = 5v -1.4 -1.0 -1.2 -0.6 -0.8 -0.2 -0.4 0 -40 0 20 -20 40 60 80 internal temperature sensor error vs. temperature max1385/86 toc29 temperature ( c) error ( c) -1.0 -0.4 -0.6 -0.8 0 -0.2 0.8 0.6 0.4 0.2 1.0 max1385/86 toc30 error ( c) external temperature sensor error vs. temperature -40 0 20 -20 40 60 80 temperature ( c) -0.100 -0.075 -0.050 -0.025 0 0.025 0.050 0.075 0.100 4.75 4.85 4.95 5.05 5.15 5.25 adc offset error vs. av dd voltage max1385/86 toc27 av dd (v) offset error (%) typical operating characteristics (continued) (gatev dd = +5.5v for the max1385, gatev dd = +11v for the MAX1386, av dd = dv dd = +5v, external v refadc = +2.5v, external v refdac = +2.5v, c ref = 0.1?, t a = +25?, unless otherwise noted.) 2.484 2.489 2.494 2.499 2.504 2.509 -40 -10 -25 5 20 35 50 65 80 internal reference vs. temperature max1385/86 toc25 temperature ( c) reference voltage (v) av dd = 5v -0.100 -0.050 -0.075 0.025 0 -0.025 0.075 0.050 0.100 -40 5 20 -25 -10 35 50 65 80 adc offset error vs. temperature max1385/86 toc26 temperature ( c) offset error (%) av dd = 5v
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 15 pin description pin name function 1 dgnd digital ground 2 safe1 safe status channel 1 output. programmable active-high or active-low. safe1 asserts when programmed channel 1 temperature threshold or current threshold has been reached. 3 a0/ csb i 2 c-compatible address 0/ spi-compatible chip select. see the digital serial interface section. in spi mode, drive a0/ csb low to select the device. 4 cnvst active-low conversion-start input. drive cnvst low to start a conversion (clock modes 01 and 11). connect cnvst to dv dd when initiating conversions through the serial interface (clock mode 00). 5 sel mode select. connect sel to dgnd to select i 2 c mode. connect sel to dv dd to select spi mode. 6 alarm alarm output. program alarm for comparator or interrupt output modes (see the alarm modes section). program alarm to assert on any combination of channel temperature or current thresholds. 7 safe2 safe status channel 2 output. programmable active-high or active-low. safe2 asserts when programmed channel 2 temperature threshold or current threshold has been reached. 8, 19, 25, 28, 35?9, 42, 46 n.c. no connection. not internally connected. 9 refdac dac reference input/output 10 refadc adc reference input/output 11 dxp1 diode positive input 1. connect to anode of temperature diode or the base and collector of an npn transistor. 12 dxn1 diode negative input 1. connect to cathode of temperature diode or the emitter of an npn transistor. 13 dxp2 diode positive input 2. connect to anode of temperature diode or the base and collector of an npn transistor. 14 dxn2 diode negative input 2. connect to cathode of temperature diode or the emitter of an npn transistor. 15 adcin1 adc input 1 16 adcin2 adc input 2 17 pgaout2 programmable-gain amplifier output 2 18 av dd analog power-supply input 20, 21, 22 agnd analog ground
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 16 ______________________________________________________________________________________ pin description (continued) pin name function 23 gategnd gate-drive amplifier ground 24 gatev dd gate-drive amplifier supply input 26 opsafe2 operating safe channel 2 input. drive opsafe2 high to clamp gate2 to agnd. 27 cs2+ current-sense positive input 2. cs2+ is the external sense resistor connection to the ldmos 2 supply. 29 cs2- current-sense negative input 2. cs2- is the external sense resistor connection to the ldmos 2 drain. 30 gate2 channel 2 gate-drive amplifier output 31 gate1 channel 1 gate-drive amplifier output 32 cs1- current-sense negative input 1. cs1- is the external sense resistor connection to the ldmos 1 drain. 33 cs1+ current-sense positive input 1. cs1+ is the external sense resistor connection to the ldmos 1 supply. 34 opsafe1 operating safe channel 1 input. drive opsafe1 high to clamp gate1 to agnd. 40 pgaout1 programmable-gain amplifier output 1 i 2 c-compatible address 2. see the digital serial interface section. 41 a2/n.c. no connection. leave unconnected in spi mode. 43 scl digital serial clock input i 2 c-compatible serial data input/output 44 sda/din spi-compatible serial data input i 2 c-compatible address 1. see the digital serial interface section. 45 a1/dout spi-compatible serial data output 47 busy device busy output. see the busy output section 48 dv dd digital supply input ep exposed pad. connect to agnd. internally connected to analog ground.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 17 v refdac v refdac sda/din scl pga registers 10-bit dac pga1 pgaout1 drv pgaout2 cs1+ cs1- gate1 opsafe2 gate2 cs2- cs2+ opsafe1 12-bit adc with t/h temp sensor conversion and scan oscillator and control adcin0 adcin1 mux dxp1 dxn1 dxp2 dxn2 pgaout2 pgaout1 register section dv dd dgnd gatev dd gategnd agnd pga2 8-bit high code external temp processing drv channel 1 dac registers safe1 safe2 alarm digital current and temperature comparators serial interface 8-bit low code 10-bit fine adjust code channel 1 dac registers 8-bit high code 8-bit low code 10-bit fine adjust code cnvst v refadc 2.5v ref 10-bit dac refdac refadc v refdac fifo memory a0/csb a1/dout a2/n.c. av dd max1385 MAX1386 functional diagram
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 18 ______________________________________________________________________________________ detailed description the max1385/MAX1386 set and control bias conditions for dual rf ldmos power devices found in cellular base stations. each device includes a high-side cur- rent-sense amplifier with programmable gains of 2, 10, and 25 to monitor the ldmos drain current over the 20ma to 5a range. two external diode-connected tran- sistors monitor the ldmos temperatures while an inter- nal temperature sensor measures the local die temperature of the max1385/MAX1386. a 12-bit adc converts the programmable-gain amplifier (pga) out- puts, external/internal temperature readings, and two auxiliary inputs. the two gate-drive channels, each consisting of 8-bit coarse and 10-bit fine dacs and a gate-drive amplifier, generate a positive gate voltage to bias the ldmos devices. the max1385 includes a gate-drive amplifier with a gain of 2 and the MAX1386 gate-drive amplifier provides a gain of 4. the 8-bit coarse and 10-bit fine dacs allow up to 18 bits of resolution. the max1385/ MAX1386 include autocalibration modes to minimize error over time, temperature, and supply voltage. the max1385/MAX1386 feature an i 2 c-/spi-compatible serial interface. both devices operate from a 4.75v to 5.25v analog supply (3.2ma supply current), a 2.7v to 5.25v digital supply (3.1ma supply current), and a 4.75v to 11.0v gate-drive supply (4.5ma supply current). power-on reset on power-up, the max1385/MAX1386 are in full power- down mode (see the sshut (write) section). to change to normal power mode, write two commands to the software shutdown register. the first command sets fullpd to 0 (other bits in the software shutdown register are ignored). a second command is needed to activate any internal blocks. the recommended sequence of com- mands to ensure reliable startup following the application of power, is given in the appendix: recommended power-up code sequence section. adc description the max1385/MAX1386 adc uses a fully differential successive approximation register (sar) conversion technique and on-chip track-and-hold (t/h) circuitry to convert temperature and voltage signals into 12-bit dig- ital results. the analog inputs accept single-ended input signals. single-ended signals are converted using a unipolar transfer function. see the adc transfer func- tion of figure 25 for more information. the internal adc block converts the results of the die temperature, remote diode temperature readings, pgaout1, pgaout2, adcin1, or adcin2 voltages according to which bits are set in the adc conversion register (see the adccon (write) section). the results of the conversions are written to fifo memory. the fifo holds up to 15 words (each word is 16 bits) with channel tags to indicate which channel the 12-bit data comes from. the fifo indicates an overflow condition and an underflow condition (read of an empty fifo) by the flag register (see the rdflag (read) section) and channel tags. the fifo always stores the most recent conversion results and allows the oldest data to be overwritten. read the latest result stored in the fifo by sending the appropriate read command byte (see the fifo (read) section). read the data stored in the fifo through the fifo read register. the fifo (read) section details which channel is being read and whether the fifo has over- flowed. analog-to-digital conversion scheduling the max1385/MAX1386 adc multiplexer scans select- ed inputs in the order shown in table 1. the adc multi- plexer skips over the items that are not selected in the analog-to-digital conversion register. when writing a conversion command before a conversion is complete, the pending conversion may be canceled. in addition, using the serial interface while the adc is converting may degrade the performance of the adc. adc clock modes the max1385/MAX1386 offer three different conver- sion/acquisition modes (known as clock modes) selec- table through the device configuration register (see the dcfig (read/write) section). clock mode 10 is reserved and cannot be used. for conversion/acquisi- tion examples and timing diagrams, see the applications information section. if the analog-to-digital conversion requires the internal reference (temperature measurement or voltage mea- surement with internal reference selected) and the ref- erence has not been previously forced on, the device inserts a worst-case delay of 81?, for the reference to settle, before commencing the analog-to-digital conver- sion. the reference remains powered up while there are pending conversions. if the reference is not forced on, it automatically powers down at the end of a scan or when conconv in the analog-to-digital conversion register is set back to 0.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 19 clock mode 00 in clock mode 00, power-up, acquisition, conversion, and power-down are all initiated by writing to the analog- to-digital conversion register and performed automati- cally using the internal oscillator. this is the default clock mode. the adc sets the busy output high, powers up, scans all requested channels, stores the results in the fifo, and then powers down. after the scan is complete, busy is pulled low and the results for all the command- ed channels are available in the fifo. clock mode 01 in clock mode 01, power-up, acquisition, conversion, and power-down are all initiated by setting cnvst low for at least 40ns. conversions are performed automati- cally using the internal oscillator. the adc sets the busy output high, powers up, scans all requested channels, stores the results in the fifo, and then pow- ers down. after the scan is complete, busy is pulled low and the results for all the commanded channels are available in the fifo. clock mode 11 in clock mode 11, conversions are initiated one at a time through cnvst in the order shown in table 1 and performed using the internal oscillator. in this mode, the acquisition time is controlled by the time cnvst is brought low. cnvst is resynchronized by the internal oscillator, which means there is a one-clock-cycle uncertainty (typically 320ns) in the exact sampling instant. different timing parameters apply depending whether the conversion is temperature, voltage, using the external reference, or using the internal reference. for a temperature conversion, set cnvst low for at least 40ns. the busy output goes high and the temper- ature conversion results are available after an addition- al 94? (when busy goes low again). thus, the worst-case conversion time of the initial temperature sensor scan (allowing the internal reference to settle) is 175?. subsequent temperature scans only take 85? worst case as the internal reference and temperature sensor circuits are already powered. for a voltage conversion while using an internal or external reference, set cnvst low for at least 2? but less than 6.7?. the busy output goes high and the conversion results are available after an additional 7.5? (typ) when busy goes low again. continuous conversion is not supported in this clock mode (see the adccon (write) section). changing clock modes during adc conversions if a change is made to the clock mode in the device configuration register while the adc is already per- forming a conversion (or series of conversions), the fol- lowing descriptions show how the max1385/MAX1386 respond: cksel = 00 and is then changed to another value the adc completes the already triggered series of conversions and then goes idle. the busy output remains high until the conversions are completed. the max1385/MAX1386 then respond in accor- dance with the new cksel mode. cksel = 01 and is then changed to another value if waiting for the initial external trigger, the max1385/MAX1386 immediately exit clock mode 01, power down the adc, and go idle. the busy output stays low and waits for the external trigger. if a conversion sequence has started, the adc com- pletes the requested conversions and then goes idle. the busy output remains high until the conver- sions are completed. the max1385/MAX1386 then respond in accordance with the new cksel mode. cksel = 11 and is then changed to another value if waiting for an external trigger, the max1385/ MAX1386 immediately exit clock mode 11, power down the adc, and go idle. the busy output stays low and waits for the external trigger. order of scan description of conversion 1 internal device temperature 2 external diode 1 temperature 3 pgaout1 for current sense 4 adcin1 5 external diode 2 temperature 6 pgaout2 for current sense 7 adcin2 table 1. order of adc conversion scan
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 20 ______________________________________________________________________________________ control logic capacitive dac adcin_ agnd control logic adcin_ agnd track mode hold/conversion mode capacitive dac figure 4. equivalent adc input circuit analog input track and hold the equivalent circuit (figure 4) shows the max1385/MAX1386 adc input architecture. in track mode, a positive input capacitor is connected to adcin_ and a negative input capacitor is connected to agnd. after the t/h enters hold mode, the difference between the sampled positive and negative input volt- ages is converted. the input capacitance charging rate determines the time required for the t/h to acquire an input signal. if the input signal? source impedance is high, the required acquisition time lengthens. any source impedance below 300 ? does not signifi- cantly affect the adc? ac performance. a high-imped- ance source can be accommodated either by lengthen- ing t acq or by placing a 1? capacitor between the positive input and agnd. the combination of the ana- log input source impedance and the capacitance at the analog input creates an rc filter that limits the analog- input bandwidth. analog-input bandwidth the adc? input-tracking circuitry has a 10mhz band- width to digitize high-speed transient events. anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 21 analog-input protection internal esd protection diodes clamp all analog inputs to av dd and agnd, allowing the inputs to swing from agnd - 0.3v to av dd + 0.3v without damage. if an analog input voltage exceeds the supplies, limit the input current to 2ma. dac description the max1385/MAX1386 include two 8-bit and 10-bit dac blocks to independently control the voltage on each ldmos gate. both 10-bit and 8-bit dacs can be automatically calibrated to minimize output error over time, temperature, and supply voltage. the 8-bit and 10-bit dacs have unipolar transfer functions and have a relationship to the output voltage by the following equation: where locode, hicode, and finecode are the low wiper (8 bits), high wiper (8 bits), and fine dac (10 bits) values written to the dac by the user. locode, hicode, and finecode represent the values in the dac input registers and may or may not be the actual values in the dac output registers depending whether autocalibration is used or not (see the 8-bit coarse- dac adjustment section). to find the actual voltage at gate_, multiply the v dacout result by 2 (max1385) or 4 (MAX1386). due to the buffer amplifiers, the voltage at gate_ cannot be set below 100mv above agnd. it is recommended that the locode for dac1 and dac2 are set so that the minimum possible output at gate_ is 200mv (max1385) and 400mv (MAX1386). the dacs can be operated to produce an 18-bit monotonic dac with 12-bit (typ) inl. write to either hicode or locode in a leapfrog fashion, without commanding autocalibration, to configure the 18-bit monotonic dac. when locode > hicode, invert the value of finecode. 8-bit coarse-dac adjustment each dac control block contains a resistor string with wipers that serve as an 8-bit coarse dac. wipers are set by writing to the appropriate dac input registers and/or using the load dac control register (ldac) commands. the output of a coarse dac is not updated until the appropriate dac output register(s) have been set. see figure 5 for the relationship between dac input registers, dac output registers, and wipers. dac output registers are not directly accessible to the user. choose which input register to write to based on whether automatic low or high calibration is desired, or if updates to the output of the dac need to be initiated immediately. in the case of automatic low or high cali- bration, a correction code is added to or subtracted from the 10-bit fine-dac input register. transfers from the dac input registers to dac output registers can occur immediately after a write to the appropriate dac input register or on a software command through the software ldac register. see the register descriptions section for bit-level descriptions of these registers. 10-bit fine-dac adjustment each dac control block contains a 10-bit fine dac that operates between the high and low wiper positions from the 8-bit coarse dac. the 10-bit fine dac also has an optional automatic calibration mode and can be updated immediately or on a software-issued command in the software ldac register. writing to the appropri- ate fine-dac input register determines whether auto- matic calibration is used and/or when the dac is updated. see figure 6 for the relationship between dac input registers, dac output registers, and the software ldac register. the fine-dac output registers are not directly accessi- ble. choose which dac input register to write to based on whether automatic fine calibration is desired, or whether updates to the output of the dac need to be ini- tiated immediately. in the case of automatic fine calibra- tion, a correction code is added to or subtracted from the input register code and transferred to the appropriate fine-dac output register. transfers from a fine-dac input register to a fine-dac output register can occur immedi- ately after a write to the appropriate dac input register or on a software command through the software ldac reg- ister. see the register descriptions section for bit-level detail of these registers. v v locode v hicode locode finecode dacout ref ref = + ? 22 2 88 10 []
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 22 ______________________________________________________________________________________ finethru_ register finecal_ register fine_ register finecalthru_ register load dac control register (ldac) to gate-drive block input registers from 8-bit coarse dac from 8-bit coarse dac fine-cal fine dac_ output register 10-bit fine dac figure 6. fine-dac register diagram hiwipe_ register lowipe_ register coarse dac_ low wiper output register thruhi_ register thrulo_ register v dacref hcal lcal low-cal load dac control register (ldac) to 10-bit fine dac coarse dac_ high wiper output register high-cal input registers figure 5. coarse-dac register diagram
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 23 adc/dac references the max1385/MAX1386 provide an internal low-noise 2.5v reference for the adcs, dacs, and temperature sensor. see the device configuration register section for information on configuring the device for external or internal reference. connect a voltage source to refadc in the 1v to av dd range when using an exter- nal adc reference. connect a voltage source to ref- dac in the 0.5v to 2.5v range when using an external dac reference. when using an external voltage refer- ence, bypass the reference pin with a 0.1? capacitor to agnd. the internal reference has a lowpass filter to reduce noise. the device allows 60? (typ) and 81? (typ) worst case for the reference to settle before permitting an ana- log-to-digital conversion. if reference mode 11 is select- ed, the required settling time is longer. in this case, the user should set at least one of dac1pd, dac2pd, or fbgon in the software shutdown register, any of which forces the reference to be permanently powered up. temperature measurements the max1385/MAX1386 measure the internal die tem- perature and two external remote-diode temperature sensors. set up a temperature conversion by writing to the analog-to-digital conversion register (see the adccon (write) section). optionally program safe1 and safe2 outputs to depend on programmed temper- ature thresholds. the max1385/MAX1386 can perform temperature mea- surements with an internal diode-connected transistor. the diode bias current changes from 66? to 4? to produce a temperature-dependent bias voltage differ- ence. the second conversion result at 4? is subtract- ed from the first at 66? to calculate a digital value that is proportional to the absolute temperature. the stored data result is the aforementioned digital code minus an offset to adjust from kelvin to celsius. the reference voltage for the temperature measure- ments is always derived from the internal reference source. temperature results are in degrees celsius (two?-complement form). the temperature-sensing circuits power up for the first temperature measurement in an analog-to-digital con- version scan. the temperature-sensing circuits remain powered until the end of the scan to avoid a possible 67? delay of internal reference power-up time for each individual temperature channel. if the continuous con- vert bit conconv is set high and the current adc channel selection includes a temperature channel, the temperature-sensor circuits remain powered up until the conconv bit is set low. the external temperature-sensor drive current ratio has been optimized for a 2n3904 npn transistor with an ide- ality factor of 1.0065. the nonideality offset is removed internally by a preset digital coefficient. use of a tran- sistor with a different ideality factor produces a propor- tionate difference in the absolute measured temperature. more details on this topic and others relat- ed to using an external temperature sensor can be found in maxim application note 1057: compensating for ideality and series resistance differences between thermal sense diodes and application note 1944: temperature monitoring using the max1253/max1254 and max1153/max1154 . high-side current-sense pgas the max1385/MAX1386 provide two high-side current- sense amplifiers with programmable gain. the current- sense amplifiers are unidirectional and provide a 5v to 30v input common-mode range. both cs1+ and cs2+ must be within the specified common-mode range for proper operation of each amplifier. the sense amplifiers measure the load current, i load , through an external sense resistor, r sense_ , between the cs_+ and cs_- inputs. the full-scale sense voltage range (v sense_ = v cs_ + - v cs_ -) depends on the pro- grammed gain, av pga_ (see the dcfig (read/write) section). the sense amplifiers provide a voltage output at pgaout_ according to the following equation: these outputs are also routed to the internal 12-bit adc so that a digital representation of the amplified voltages can be read through the fifo. the pga scales the sensed voltages to fit the input range of the adc. program the pga with gains of 2, 10, and 25 by setting the pgset_ bits (see the dcfig (read/write) section). the input stages have nominal input offset voltages of 0mv that can be adjusted by a trim dac (not shown in the functional diagram ) over the -3mv to +3mv range in 25? steps. autocalibration can be used to control the trim dac to minimize the effective channel input offset voltage (see the pgacal (write) section). the pga feedback network is referenced to agnd. alarm output the state of alarm is logically equivalent to the inclu- sive or of safe1 and safe2. the exception to this statement is when alarm is configured for output inter- rupt mode (see the alarm modes section). when in out- put-interrupt mode, alarm stays in its asserted state until its associated flag is cleared by reading from the vavvv pgaout pga cs cs ____ () =+ ??
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 24 ______________________________________________________________________________________ alarm output asserted when measured value rises above this level range of values that do not cause an alarm highest possible threshold value (default value for high threshold register) alarm output deasserted when measured value falls below this level* high threshold low threshold lowest possible threshold value (default value for high threshold register) alarm output deasserted when measured value rises above this level* alarm output asserted when measured value falls below this level built-in 8 to 64 lsbs of hysteresis built-in 8 to 64 lsbs of hysteresis *only when alarm is configured for output-comarator mode. when in output-interrupt mode, flag register must be read for alarm to be deasserted. figure 7. window-threshold-mode diagram flag register. configure alarm for open-drain/push- pull and active-high/active-low by setting the respective bits in the hardware alarm configuration register. safe1/safe2 outputs set up the safe1 and safe2 outputs to allow wired- or/and-type logic functions or to create additional interrupt-type signals to replace or supplement the existing alarm output. safe1 and safe2 do not have any internal pullup/pulldown devices. the safe1 and safe2 output buffers are cmos-com- patible, noninverting, output buffers capable of driving to within 0.5v of either digital rail. the safe1 and safe2 outputs power up as active-high cmos outputs with standard logic levels. configure the safe1 and safe2 outputs for open-drain or push-pull by setting the appropriate bits in the hardware alarm configuration register. when configuring safe1 and safe2 as open-drain outputs, an external pullup resis- tor is required. busy output the busy output is forced high to show that the max1385/MAX1386 are busy for a variety of reasons: the adc is in the middle of a user-commanded con- version cycle (but not in continuous convert mode) the adc is in the middle of an internally triggered conversion cycle (for a self-calibration measurement) the device is in the middle of dac calibra- tion calculations the device is in the middle of power-up initialization one of the pga channels is undergoing self-calibration the serial interface remains active regardless of the state of the busy output. wait until busy goes low to read the current conversion data from the fifo. when busy is high as a result of an adc conversion, do not enter a second conversion command until busy has gone low to indicate the previous conversion is com- plete. the rising edge of busy occurs on the next inter- nal oscillator clock after the start of a new conversion (either by cnvst or an interface command).
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 25 in single-conversion mode (cksel = 11), the busy signal remains high until the adc has completed the current conversion (not the entire scan, just the current conversion), the data has been moved into the fifo, and the alarm limits for the channel have been checked (if enabled). in multiple-conversion mode (cksel = 01 or cksel = 00), the busy signal remains high until all channels have been scanned and the data from the final channel has been moved into the fifo and checked for alarm limits (if enabled). in continuous-con- version mode (conconv = 1), the busy signal does not go high as a result of adc conversions; however, busy does go high when conconv is removed and remains high until the current scan is complete and the adc sequence halts. after commanding any of the dac autocalibration compo- nents, wait for busy to go low before setting oscpd to 1. alarm modes the max1385/MAX1386 contain several programmable modes for configuring outputs alarm, safe1, and safe2 behavior. window-threshold mode allows safe_ to assert when the temperature/current is too high or too low (outside the window). hysteresis-threshold mode allows safe_ to assert when the temperature/ current is too high, and then to deassert when the tem- perature/current falls back to an appropriate level. alarm asserts when safe1 and/or safe2 asserts. program alarm for output-comparator mode to stay asserted after an alarm condition until temperature/cur- rent levels are back below programmed thresholds. program alarm for output-interrupt mode to stay asserted after an alarm condition until the flag register is read. window-threshold mode in window-threshold mode, adc readings of current/temperature are compared to the configured current/temperature low/high thresholds that are pro- grammed to cause an alarm condition. if an adc read- ing falls out of the configured window and alarm is configured for output-comparator mode, alarm asserts until the current/temperature reading falls back into the window (past the built-in hysteresis). if an adc reading falls out of the configured window and alarm is configured for output-interrupt mode, alarm asserts until the flag register is read. set the amount of built-in hysteresis from 8 lsbs to 64 lsbs (see the almscfg (read/write) section). see figures 7 and 8. measurement value (temperature or current) high threshold built-in hysteresis built-in hysteresis low threshold alarm output output- comparator mode (active low) output- interrupt mode (active low) flag register read flag register read flag register read time time figure 8. window-threshold-mode timing diagram
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 26 ______________________________________________________________________________________ hysteresis-threshold mode in hysteresis-threshold mode, adc readings of current/temperature are compared to the configured current/temperature low/high thresholds that are pro- grammed to cause an alarm condition. if an adc read- ing exceeds its respective configured threshold and alarm is configured for output-comparator mode, alarm asserts until the current/temperature reading falls back below its respective threshold. if an adc reading exceeds its respective configured threshold and alarm is configured for output-interrupt mode, alarm asserts until the flag register is read. see figures 9 and 10. register descriptions communicate with the max1385/MAX1386 through the i 2 c/spi-compatible serial interface. complete read and write operations consist of slave address bytes, com- mand bytes, and data bytes. the following register descriptions cover the contents of command bytes and data bytes. see the digital serial interface section for a detailed description of how to construct full read and write operations. all registers are volatile and are reset to default states upon removal of power. these default states are referred to as power-on reset (por) states. all accessible max1385/MAX1386 registers are shown in table 2. th1 and th2 (read/write) write to channel 1 and channel 2 high temperature threshold registers by sending the appropriate write command byte followed by data bits d15?0 (see table 3). bits d15?12 are don? care. read channel 1 and channel 2 high-temperature thresholds by sending the appropriate read command byte. channel 1 and channel 2 temperature threshold registers are com- pared to temperature readings from the remote diode connected transistors. temperature data is in two?-com- plement format and the lsb corresponds to 1/8? (see figure 26 for the temperature transfer function). tl1 and tl2 (read/write) write to channel 1 and channel 2 low-temperature- threshold registers by sending the appropriate write command byte followed by data bits d15?0 (see table 4). bits d15?12 are don? care. read channel 1 and channel 2 low-temperature thresholds by sending the appropriate read command. channel 1 and channel 2 temperature threshold registers are compared to tem- perature readings from the remote diode connected tran- sistors. temperature data is in two?-complement format and the lsb corresponds to 1/8? (see figure 26 for the temperature transfer function). alarm output asserted when measured value rises above this level range of values that do not cause an alarm highest possible threshold value (default value for high threshold register) high threshold low threshold lowest possible threshold value (default value for low threshold register) alarm output asserted when measured value falls below this level *only when alarm is configured for output-comarator mode. when in output-interrupt mode, flag register must be read for alarm to be deasserted. figure 9. hysteresis-threshold-mode diagram
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 27 hex command register description mnemonic write read analog-to-digital conversion adccon 62 channel 1 high-current threshold ih1 24 a4 channel 1 high-temperature threshold th1 20 a0 channel 1 low-current threshold il1 26 a6 channel 1 low-temperature threshold tl1 22 a2 channel 2 high-current threshold ih2 2c ac channel 2 high-temperature threshold th2 28 a8 channel 2 low-current threshold il2 2e ae channel 2 low-temperature threshold tl2 2a aa coarse dac1 high wiper input hiwipe1 34 b4 coarse dac1 low wiper input lowipe1 36 b6 coarse dac1 write-through high wiper input thruhi1 74 b4 coarse dac1 write-through low wiper input thrulo1 76 b6 coarse dac2 high wiper input hiwipe2 3a ba coarse dac2 low wiper input lowipe2 3c bc coarse dac2 write-through high wiper input thruhi2 7a ba coarse dac2 write-through low wiper input thrulo2 7c bc device configuration dcfig 30 b0 fifo memory fifo 80 fine dac1 input read rdfine1 b8 fine dac1 input register with autocalibration finecal1 38 fine dac1 input without autocalibration fine1 50 fine dac1 write-through input with autocalibration finecalthru1 78 fine dac1 write-through input without autocalibration finethru1 52 fine dac2 input read rdfine2 be fine dac2 input register with autocalibration finecal2 3e fine dac2 input without autocalibration fine2 54 fine dac2 write-through input with autocalibration finecalthru2 7e fine dac2 write-through input without autocalibration finethru2 56 flag rdflag ea hardware alarm configuration almhcfg 60 e0 pga calibration control pgacal 4e software clear sclr 68 software ldac ldac 66 software shutdown sshut 64 software alarm configuration almscfg 32 b2 table 2. register listing (see appendix: recommended power-up code sequence section)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 28 ______________________________________________________________________________________ ih1 and ih2 (read/write) write to channel 1 and channel 2 high-current- threshold registers by sending the appropriate write command byte followed by data bits d15?0 (see table 5). bits d15?12 are don? care. read channel 1 and channel 2 high-current thresholds by sending the appropriate read command byte. channel 1 and channel 2 current-threshold registers are compared to adc readings at pgaout1 and pgaout2. use the following equation to find the required threshold code for a specified threshold current: where i drain is the current threshold in amperes, r sense is the sense resistor, av pga is the voltage gain of the pga, v refadc is the adc reference voltage, and i thresh is the resulting threshold register value in decimal. il1 and il2 (read/write) write to channel 1 and channel 2 low-current- threshold registers by sending the appropriate write command byte followed by data bits d15?0 (see table 6). bits d15?12 are don? care. read channel 1 and channel 2 low-current thresholds by sending the appropriate read command byte. channel 1 and channel 2 low-current threshold registers are com- pared to adc readings at pgaout1 and pgaout2. iirav v thresh drain sense pga refadc = 4096 flag register read flag register read time time measurement value (temperature or current) high threshold low threshold alarm output output- comparator mode (active low) output- interrupt mode (active low) figure 10. hysteresis-threshold-mode timing diagram d15 d14 d13 d12 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) por xxxx 0 111111111 1 1 bit value (?) x x x x -256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 +0.125 table 3. th1 and th2 (read/write) x = don? care.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 29 use the following equation to find the required thresh- old code for a specified threshold current: where i drain is the current threshold in amperes, r sense is the sense resistor, av pga is the voltage gain of the pga, v refadc is the adc reference voltage, and i thresh is the resulting threshold register value in decimal. dcfig (read/write) select pga gain settings, clock modes, and dac and adc reference modes by sending the appropriate write command byte followed by data bits d15?0 (see table 7). bits d15?10 are don? care. read the device configuration register by sending the appropriate read command byte. program pg2set1 and pg2set0 to set channel 2? current-sense amplifier gain (see table 7a). program pg1set1 and pg1set0 to set channel 1? current-sense amplifier gain (see table 7a). set cksel1 and cksel0 to determine the conversion and acquisition timing clock modes (see table 7b). see the adc clock modes section for a functional description of each clock mode. set refadc1 and refadc0 to select external/internal reference for the adc (see table 7c). set refdac1 and refdac0 to select exter- nal/internal reference for both dacs (see table 7d). when mode 11 is selected, the external capacitor that is connected to the refadc is charged by a resistor with a typical value of 400k ? . this time constant needs to be allowed for powering up the reference. avoid leakage paths to refadc. almscfg (read/write) the software alarm configuration register controls the behavior of outputs safe1, safe2, and alarm. write to the software alarm configuration register by sending the appropriate write command byte followed by data bits d15?0 (see table 8). bits d15?12 are don? care. read the software alarm configuration register by sending the appropriate command byte. set almsclr to 1 to immediately set all temperature/ current threshold registers to their por state. in addi- tion, temperature-/current-related bits of the flag regis- ter are also reset to their por state. the almsclr resets to 0 immediately after a write. set alarmcmp to 1 to enable output-comparator mode for alarm and to 0 to enable output-interrupt mode for alarm (see the iirav v thresh drain sense pga refadc = 4096 d15 d14 d13 d12 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) por xxxx1 000000000 0 0 bit value (?) x x x x -256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 +0.125 table 4. tl1 and tl2 (read/write) x = don? care. d15 d14 d13 d12 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) por xxxx 1 1111111111 1 bit valuexxxx table 5. ih1 and ih2 (read/write) x = don? care. d15 d14 d13 d12 d11 (msb) d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 (lsb) por xxxx 0 0 0 0 0 0 0 0 0 0 0 0 bit value x x x x table 6. il1 and il2 (read/write) x = don? care.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 30 ______________________________________________________________________________________ alarm modes section). setting alarmcmp does not affect safe1 and safe2 outputs. program alarmhyst1 and alarmhyst0 to set the amount of built-in hysteresis used in window-threshold mode. see the alarm output and safe1/safe2 outputs sections for a description of the relationship between alarm and safe1 and safe2. set talarm2 to 1 to allow channel 2 temperature measurements to control the state of safe2 and alarm based on channel 2 temperature thresholds. set twin2 to 0 to enable hys- teresis-threshold mode and to 1 to enable window- threshold mode for channel 2 temperature measurements (see the alarm modes section). set ialarm2 to 1 to allow channel 2 current measurements to control the state of safe2 and alarm based on channel 2 current thresholds. set iwin2 to 0 to enable hysteresis-threshold mode and to 1 to enable window- threshold mode for channel 2 current measurements. set talarm1 to 1 to allow channel 1 temperature mea- surements to control the state of safe1 and alarm based on channel 1 temperature thresholds. set twin1 to 0 to enable hysteresis-threshold mode and to 1 to enable window-threshold mode for channel 1 tempera- ture measurements (see the alarm modes section). set ialarm1 to 1 to allow channel 1 current measurements to control the state of safe1 and alarm based on channel 1 current thresholds. set iwin1 to 0 to enable hysteresis-threshold mode and to 1 to enable window- threshold mode for channel 1 current measurements. hiwipe1 and hiwipe2 (read/write) write to the coarse dac1/dac2 high wiper input reg- ister by sending the appropriate write command byte followed by data bits d15?0 (see table 9). bits d14?8 are don? care. read the coarse dac1/dac2 high wiper input register by sending the appropriate read command byte. the dac output is not updated until an ldac command is issued, at which point the bit name data bit por function x d15?10 x don? care pg2set1 d9 0 pga 2 gain-setting pg2set0 d8 0 pga 2 gain-setting pg1set1 d7 0 pga 1 gain-setting pg1set0 d6 0 pga 1 gain-setting cksel1 d5 0 clock mode and cnvst configuration cksel0 d4 0 clock mode and cnvst configuration refadc1 d3 0 adc reference select refadc0 d2 0 adc reference select refdac1 d1 0 dac reference select refdac0 d0 0 dac reference select table 7. dcfig (read/write) pg_set1 pg_set0 function 0 0 pga_ gain of 2 0 1 pga_ gain of 10 1 x pga_ gain of 25 table 7a. gain-setting modes x = don? care. cksel1 cksel0 conversion clock acquisition/ sampling 0 0 internal internally timed acquisitions and conversions. conversions started by a write to the analog- to-digital conversion register or setting the conconv bit. 0 1 internal internally timed acquisitions and conversions. conversions begin with a high-to-low transition at cnvst . 1 0 reserved. do not use. 1 1 internal externally timed acquisitions by cnvst . conversions internally timed. table 7b. clock modes refadc1 refadc0 description 0x external. bypass refadc with a 0.1? capacitor to agnd. 10 internal. leave refadc unconnected. 11 internal. connect a 0.1? capacitor to refadc for better noise performance. table 7c. adc reference selection x = don? care.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 31 dac input register is transferred to the appropriate dac output register. automatic calibration of the high wiper is initiated if the hcal bit in the dac input register is set to 1 when the appropriate ldac command is issued. lowipe1 and lowipe2 (read/write) write to the coarse dac1/dac2 low wiper input regis- ter by sending the appropriate command byte followed by data bits d15?0 (see table 10). bits d14?8 are don? care. read the coarse dac1/dac2 low wiper input register by sending the appropriate read com- mand byte. the dac output is not updated until an ldac command is issued, at which point the dac input register is transferred to the appropriate dac out- put register. automatic calibration of the low wiper is initiated if the lcal bit in the dac input register is set to 1 when the appropriate ldac command is issued. finecal1 and finecal2 (write) write to the fine dac1/dac2 input register with auto- calibration by sending the appropriate write command byte followed by data bits d15?0 (see table 11). bits d15?10 are don? care. a write to these registers trig- gers the autocalibration but does not automatically update the output of the dac. write to the software ldac register (ldac) to transfer the fine dac input register contents to the fine dac output register, thereby updating the output of the dac. por contents for these registers are all zeros. read the dac input register values written to fine dac1 and dac2 input registers through the fine dac1/dac2 input read reg- ister. these read registers contain the latest user-write to any fine dac1 or fine dac2 input read register and do not contain autocalibration-corrected values. pgacal (write) write to the pga calibration control register to calibrate pga1 and pga2 internal amplifiers. write to the pga calibration control register by sending the appropriate write command byte followed by data bits d15?0 (see table 12). bits d15?8 are reserved and must be set to 0. bits d7?3 are don? care. set firstb to 1 to enable tracking-calibration mode, and to 0 to enable acquisi- tion-calibration mode. during an offset calibration trial, for either mode, the corresponding pgaout_ is put into hold, which pro- duces a pedestal error for 67? typically and busy is set to 1. in acquisition mode, the calibration routine operates continuously, first on channel 1 and then on channel 2, until the channel-input offset voltage error has been reduced to within 50?. the time taken for both channels to complete acquisition depends upon the initial channel offset voltage error but should never be longer than 112ms. in tracking mode, a pair of offset calibration trials, first on channel 1 and then on channel 2, are made each time docal is set to 1 or every 20ms if the selftime bit is set to 1. to reject noise, the offset trim dac code (not shown in the functional diagram ) only increments or decrements after the results of 16 calibration trials have been averaged. set firstb to 0 and docal to 1 to initiate an acquisi- tion calibration. acquisition must be done before track- ing the first time a pga calibration is commanded. set firstb to 1, docal to 1, and selftime to 0 to trigger an offset calibration trial on pga1 and pga2. at the end of the routine, docal returns to 0. set firstb to 1, docal to 1 (optional to trigger calibration once immediately before selftime starts periodic calibra- tions), and selftime to 1, just once, to trigger periodic offset-calibration trials (approximately every 20ms). set selftime to 0 to halt the periodic calibration. fine1 and fine2 (write) write to the fine dac1/dac2 input register without auto- calibration by sending the appropriate write command byte followed by data bits d15?0 (see table 13). bits d15?10 are don? care. a write to these registers does not trigger the autocalibration and does not automatically update the output of the dac. write to the software ldac register (ldac) to transfer the dac input register contents to the fine dac output register, thereby updat- ing the output of the fine dac. por contents for these registers are all zeros. read the dac input register val- ues written to fine dac1 and dac2 input registers through the fine dac1/dac2 input read register. these read registers contain the latest user-write to any fine dac1 or fine dac2 input read register and do not con- tain autocalibration corrected values. finethru1 and finethru2 (write) write to the fine dac1/dac2 write-through input reg- ister without autocalibration by sending the appropriate write command byte followed by data bits d15?0 (see refdac1 refdac0 description 0x external. bypass refdac with a 0.1? capacitor to agnd. 10 internal. leave refdac unconnected. 11 internal. connect a 0.1? capacitor to refdac for extra decoupling and better noise performance. table 7d. dac reference selection x = don? care.
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 32 ______________________________________________________________________________________ table 14). bits d15?10 are don? care. a write to these registers does not trigger the autocalibration but imme- diately updates the output of the dac by transferring the dac input register to the dac output register (writ- ing through the input register). por contents for these registers are all zeros. read the dac input register val- ues written to fine dac1 and dac2 input registers through the fine dac1/dac2 input read register. these read registers contain the latest user write to any fine dac1 or fine dac2 input read register and do not contain autocalibration corrected values. bit name data bit por function x d15?12 x don? care almsclr d11 0 1 = temp/current thresholds set to por state 0 = temp/current thresholds unaffected alarmcmp d10 0 1 = alarm in output-comparator mode 0 = alarm in output-interrupt mode alarmhyst1 d9 0 alarmhyst0 d8 0 thresholds hysteresis (alarmhyst1 is msb) 00 = 8 lsbs of hysteresis 01 = 16 lsbs of hysteresis 10 = 32 lsbs of hysteresis 11 = 64 lsbs of hysteresis talarm2 d7 0 1 = safe2 and alarm dependent on channel 2 temperature 0 = safe2 and alarm not dependent on channel 2 temperature twin2 d6 0 1 = channel 2 temperature thresholds are in window-threshold mode 0 = channel 2 temperature thresholds are in hysteresis-threshold mode ialarm2 d5 0 1 = safe2 and alarm dependent on channel 2 current 0 = safe2 and alarm not dependent on channel 2 current iwin2 d4 0 1 = channel 2 current thresholds are in window-threshold mode 0 = channel 2 current thresholds are in hysteresis-threshold mode talarm1 d3 0 1 = safe1 and alarm dependent on channel 1 temperature 0 = safe1 and alarm not dependent on channel 1 temperature twin1 d2 0 1 = channel 1 temperature thresholds are in threshold-window mode 0 = channel 1 temperature thresholds are in hysteresis-threshold mode ialarm1 d1 0 1 = safe1 and alarm dependent on channel 1 current 0 = safe1 and alarm not dependent on channel 1 current iwin1 d0 0 1 = channel 1 current thresholds are in window-threshold mode 0 = channel 1 current thresholds are in hysteresis-threshold mode table 8. almscfg (read/write) x = don? care. bit name data bit por function hcal d15 1 1 = high wiper autocalibration. 0 = no high wiper autocalibration. d14?8 x don? care. d7?0 0000 0000 8-bit coarse high wiper dac input code. d7 is the msb. table 9. hiwipe1 and hiwipe2 (read/write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 33 almhcfg (read/write) the hardware alarm configuration register controls safe1, safe2, and alarm outputs. write to the hardware alarm configuration register by sending the appropriate write command byte followed by data bits d15?0 (see table 15). bits d15?8 are don? care. read the hardware alarm configuration register by sending the appropriate read command byte. set setsafe1 to 1 to immediately force safe1 active. this is especially useful when safe1 is connected to opsafe1, giving the user software control over shut- ting down the ldmos transistor. set setsafe1 to 0 for normal operation. setsafe2 has the same functionality as setsafe1 but for channel 2. set alarmpol to 1 to configure alarm active-low. set it to 0 to configure alarm active-high. set alarmopn to 1 to configure alarm open-drain. set it to 0 to config- ure alarm push-pull. set safe1pol to 1 to configure safe1 for active-low, and to 0 for active-high. set safe2pol to 1 to configure safe2 for active-low, and to 0 for active-high. set safe1opn to 1 to configure safe1 for open-drain, and to 0 for push-pull. set safe2opn to 1 to configure safe2 for open-drain, and to 0 for push-pull. when connecting safe1 and safe2 outputs to opsafe1 and opsafe2 inputs, configure the device as follows: 1) set safe1pol and safe2pol to 0s. 2) set safe1opn and safe2opn to 0s. this ensures that when safe1 and safe2 are assert- ed, and connected to opsafe1 and opsafe2, the ldmos transistors are shut off. adccon (write) the analog-to-digital conversion register selects which inputs to the adc are converted. write to the analog-to- digital conversion register by sending the appropriate write command byte followed by data bits d15?0 (see table 16). bits d15?12 are don? care. bits d11?8 are reserved bits and need to be set to 0. read the results of the conversions in the fifo by sending the appropriate read command byte. see the adc description section for a complete description of the adc. set conconv to 1 to convert selected inputs to the adc continuously and to 0 to convert selected inputs to the adc only once. set adcsel2 to 1 to select volt- ages at adcin2 to be converted. set iext2 to 1 to select voltages at pgaout2 to be converted. set bit name data bit por function lcal d15 1 1 = low wiper autocalibration. 0 = no low wiper autocalibration. d14?8 x don? care. d7?0 0000 0000 8-bit coarse low wiper dac input code. d7 is the msb. table 10. lowipe1 and lowipe2 (read/write) bit name data bit reset state function reserved d15?8 0 reserved. set to 0. x d7?3 x don? care. firstb d2 0 1 = tracking calibration mode. 0 = acquisition calibration mode. docal d1 0 1 = initiate the calibration defined by firstb (one time). 0 = do not initiate a calibration. selftime d0 0 1 = initiate periodic calibrations defined by firstb (every 15ms). 0 = stop periodic calibrations. table 12. pgacal (write) data bit por function d15?10 x don? care. d9?0 00 0000 0000 10-bit fine dac input code. d9 is the msb. table 11. finecal1 and finecal2 (write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 34 ______________________________________________________________________________________ text2 to 1 to select the temperature at external diode 2 to be converted. set adcsel1 to 1 to select voltages at adcin1 to be converted. set iext1 to 1 to select volt- ages at pgaout1 to be converted. set text1 to 1 to select the temperature at external diode 1 to be con- verted. set tint to 1 to select the internal temperature of the max1385/MAX1386 to be converted. during continuous conversions (conconv = 1), the adc does not trigger the busy signal. when conconv is set to 0, the current scan (not just the current conversion) is completed and the adc waits for the next command. during continuous conversions, the fifo overflows if the user does not read it quickly enough. when the fifo overflows, it contains a mixture of old and new conversion results (see the rdflag (read) section). continuous conversion mode is only available in clock modes 00 and 01. sshut (write) the software shutdown register shuts down all internal blocks at once or the dac, adc, and pga blocks indi- vidually. write to the software shutdown register by sending the appropriate write command byte followed by data bits d15?0 (see table 17). bits d15?8 and d6, d5, and d4 are don? care. set fullpd to 1 to shut down all internal blocks and reduce the av dd supply current to 0.2?. fullpd is set to 1 at power-up. to change to normal power mode, write two commands to the software shutdown register. the first command sets fullpd to 0 (other bits in the software shutdown register are ignored). a second command is needed to activate any internal blocks. fullpd overrides all other shutdown bits; however, all shutdown bits retain their data when fullpd is set to 1. this means that if dac1 and pga1 are shut down before fullpd is set to 1, they remain shut down after fullpd is set to 0 again. set fbgon to 1 to force the internal bandgap refer- ence to be powered at all times. set fbgon to 0 to transfer power-down control of the internal reference to the adc. in the event of dac1pd or dac2pd being set to 0, the internal bandgap is forced on. set oscpd to 1 to shut down the internal oscillator. when the oscillator is shut down, the adc ceases conversions and internal pga calibration halts. any interface command restarts the oscillator and allows the system to resume from where it left off. set dac2pd to 1 to shut down dac2 and pga2. set dac1pd to 1 to shut down dac1 and pga1. dac1pd and dac2pd power down the individ- ual blocks regardless of additional commands; howev- er, writes are still permitted to the dacs and pgas. for maximum accuracy, do not command a dac calibra- tion while a dac is powered down or powering up. ldac (write) the software ldac register controls the loading of the dac output registers with values from dac input regis- ters, allowing the user to update several changes to the dac all at once (see table 18). write to the software ldac register by sending the appropriate write com- mand byte followed by data bits d15?0. bits d15?6 are don? care. any bit set to 1 in the software ldac register is immediately set to 0 thereafter. data bit por function d15?10 x don? care. d9?0 00 0000 0000 10-bit fine dac input code. d9 is the msb. table 13. fine1 and fine2 (write) data bit por function d15?10 x don? care. d9?0 00 0000 0000 10-bit fine dac input code. d9 is the msb. table 14. finethru1 and finethru2 (write) bit name data bit por function x d15?8 x don? care setsafe1 d7 0 1 = force safe1 active immediately 0 = normal operation setsafe2 d6 0 1 = force safe2 active immediately 0 = normal operation alarmpol d5 0 1 = alarm is active-low 0 = alarm is active-high alarmopn d4 0 1 = alarm is open-drain 0 = alarm is push-pull safe1pol d3 0 1 = safe1 is active-low 0 = safe1 is active-high safe1opn d2 0 1 = safe1 is open-drain 0 = safe1 is push-pull safe2pol d1 0 1 = safe2 is active-low 0 = safe2 is active-high safe2opn d0 0 1 = safe2 is open-drain 0 = safe2 is push-pull table 15. almhcfg (read/write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 35 set finech2 to 1 to load the fine dac2 output register with the latest write to dac2 input registers fine2 or finecal2. this means that if fine2 is written to after finecal2, fine2 is sent to the fine dac2 output regis- ter (no calibration code) when finech2 is set to 1. set highch2 to 1 to load dac input register hiwipe2 into the coarse dac2 high wiper register. autocalibration of the dac2 high wiper occurs if the hcal bit in hiwipe2 is set to 1. set lowch2 to 1 to load dac input register lowipe2 into the coarse dac2 low wiper register. autocalibration of the dac2 low wiper occurs if the lcal bit in lowipe2 is set to 1. set finech1 to 1 to load the fine dac1 output register with the latest write to dac input registers fine1 or finecal1. if finecal1 is written to after fine1, finecal1 is sent to the fine dac1 output register (with calibration code) when finech1 is set to 1. set high- ch1 to 1 to load dac input register hiwipe1 into the coarse dac1 output register. autocalibration of the dac1 high wiper occurs if the hcal bit in hiwipe1 is set to 1. set lowch1 to 1 to load dac input register lowipe1 into the coarse dac1 output register. autocalibration of the dac1 low wiper occurs if the lcal bit in lowipe1 is set to 1. sclr (write) write to the software clear register to reset the dacs and fifo to their por states (see table 19). write to the software clear register by sending the appropriate write command byte followed by data bits d15?0. bits d15?10 are don? care. a write to bits d5?0 in the software clear register immediately changes the appro- priate dac output to its power-on state (regardless of ldac). to reset all registers at once, set fullreset to 0 and armreset to 1. next set fullreset to 1 and armreset to 0. this 2-byte reset operation protects the registers from being fully reset by inadvertent user writes. after a full reset, the device is in shutdown mode and the sshut register needs to be written to for full operation. set clfifo to 1 to clear the entire 15-word fifo and fifo-associated flag bits in the flag register. set highcl2 to 1 to reset the coarse dac2 high wiper output and input registers to their por states. set lowcl2 to 1 to reset the coarse dac2 high wiper output and input registers to their por states. set finecl1 to 1 to reset fine dac1 output and input reg- isters to their por states. set highcl1 to 1 to reset the coarse dac1 high wiper output and input regis- ters to their por states. set lowcl1 to 1 to reset the bit name data bit por function x d15?12 x don? care reserved d11?8 0 reserved; set these bits to 0 conconv d7 0 1 = continuous conversions (repeated scans) 0 = noncontinuous conversions (one scan) adcsel2 d6 0 1 = select voltages at adcin2 to be converted 0 = do not select voltages at adcin2 to be converted iext2 d5 0 1 = select voltages at pgaout2 to be converted 0 = do not select voltages at pgaout2 to be converted text2 d4 0 1 = select temperature at remote diode 2 to be converted 0 = do not select temperature at remote diode 2 to be converted adcsel1 d3 0 1 = select voltages at adcin1 to be converted 0 = do not select voltages at adcin1 to be converted iext1 d2 0 1 = select voltages at pgaout1 to be converted 0 = do not select voltages at pgaout1 to be converted text1 d1 0 1 = select temperature at remote diode 1 to be converted 0 = do not select temperature at remote diode 1 to be converted tint d0 0 1 = select internal temperature of device to be converted 0 = do not select internal temperature of device to be converted table 16. adccon (write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 36 ______________________________________________________________________________________ coarse dac1 low wiper output and input registers to their por states. set finecl2 to 1 to reset fine dac2 output and input registers to their por states. thruhi1 and thruhi2 (read/write) write to the coarse dac1/dac2 write-through high wiper input register by sending the appropriate write command byte followed by data bits d15?0 (see table 20). bits d15?8 are don? care. writing to one of these registers automatically writes through to the appropriate dac output register, thereby updating the dac output immediately. writing to one of these regis- ters does not trigger automatic high wiper calibration. read the coarse dac1/dac2 write-through high wiper input register by sending the appropriate read command byte. thrulo1/thrulo2 (read/write) write to the coarse dac1/dac2 write-through low wiper input register by sending the appropriate write command byte followed by data bits d15?0 (see table 21). bits d15?8 are don? care. writing to one of these registers automatically writes through to the appropriate dac output register, thereby updating the dac output immediately. writing to one of these regis- ters does not trigger automatic low wiper calibration. read the coarse dac1/dac2 write-through low bit name data bit por function x d15?8 x don? care fullpd d7 1 1 = shut down all internal blocks 0 = do not shut down all internal blocks x d6, d5, d4 x don? care fbgon d3 0 1 = force internal bandgap reference to be powered always 0 = let the adc control power-down of the internal reference oscpd d2 0 1 = shut down the internal oscillator 0 = do not shut down the internal oscillator dac2pd d1 1 1 = power down dac2 0 = do not power down dac2 dac1pd d0 1 1 = power down dac1 0 = do not power down dac1 table 17. sshut (write) bit name data bit por function x d15?6 x don? care finech2 d5 n/a 1 = update fine dac2 with fine2 or finecal2 0 = do not update dac2 highch2 d4 n/a 1 = update coarse dac2 with hiwipe2 0 = do not update dac2 lowch2 d3 n/a 1 = update coarse dac2 with lowipe2 0 = do not update dac2 finech1 d2 n/a 1 = update fine dac1 with fine1 or finecal1 0 = do not update dac1 highch1 d1 n/a 1 = update coarse dac1 with hiwipe1 0 = do not update dac1 lowch1 d0 n/a 1 = update coarse dac1 with lowipe1 0 = do not update dac1 table 18. ldac (write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 37 wiper input register by sending the appropriate read command byte. finethrucal1 and finethrucal2 (write) write to the fine dac1/dac2 write-through input reg- ister with autocalibration by sending the appropriate write command byte followed by data bits d15?0 (see table 22). bits d15?10 are don? care. a write to these registers not only triggers the autocalibration but imme- diately updates the output of the dac by transferring the dac input register with correction code to the fine dac output register. por contents for these registers are all zeros. read the dac input register values writ- ten to fine dac1 and dac2 input registers through the fine dac1/dac2 input read register. these read reg- isters contain the latest user-write to any fine dac1 or fine dac2 input register and do not contain autocali- bration-corrected values. fifo (read) read the oldest result in the fifo by sending the appropriate read command byte and reading out data bits d15?0 (see table 23). bits d15?12 are channel tag bits that indicate the source of the conversion. bits d11?0 contain the conversion result. reading from the fifo when the fifo is empty results in the current contents of the flag read register to be sent. rdfine1 and rdfine2 (read) read the fine dac1/dac2 input read register by sending the appropriate read command byte and read- ing out data bits d15?0 (see table 24). data contains the last write to any fine dac1/dac2 input registers and does not contain autocalibration-corrected values. rdflag (read) the flag register contains important system information regarding adc/fifo status and alarm conditions. read the flag register by sending the appropriate read com- mand byte and reading out data bits d15?0 (see table 25). bits d15?12 are don? care. adcbusy is set to 1 when the adc is busy, an alarm value is being checked, or the adc results are being loaded into the fifo. adcbusy is set to 0 when the adc has completed all the conversions in the current scan. alubusy is set to 1 when the alu is busy and set to 0 when it is not. alubusy is set to 1 for 134? at power- up for initialization. fifoemp is set to 1 when the fifo is empty and set to 0 when the fifo contains data. writing to the appropriate bit in the software clear reg- ister empties the fifo and sets the fifoemp bit to 1. bit name data bit por function x d15?10 x don? care fullreset d9 n/a armreset d8 0 full reset of all dac registers is a two write operation: 1) fullreset = 0, armreset = 1 2) fullreset = 1, armreset = 0 x d7 x don? care clfifo d6 n/a 1 = clear fifo and fifo flag bits 0 = do not clear fifo or fifo flag bits highcl2 d5 n/a 1 = reset coarse dac2 high wiper to its por state 0 = do not reset coarse dac2 high wiper to its por state lowcl2 d4 n/a 1 = reset coarse dac2 low wiper to its por state 0 = do not reset coarse dac2 low wiper to its por state finecl1 d3 n/a 1 = reset fine dac1 to its por state 0 = do not reset fine dac1 to its por state highcl1 d2 n/a 1 = reset coarse dac1 high wiper to its por state 0 = do not reset coarse dac1 high wiper to its por state lowcl1 d1 n/a 1 = reset coarse dac1 high wiper to its por state 0 = do not reset coarse dac1 high wiper to its por state finecl2 d0 n/a 1 = reset fine dac2 to its por state 0 = do not reset fine dac2 to its por state table 19. sclr (write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 38 ______________________________________________________________________________________ fifoover is set to 1 when the fifo overflows. fifoover is set to 0 after reading the flag register. all threshold-related bits in the flag register can be cleared at once by writing to the almsclr bit in the software alarm configuration register (see the almscfg (read/write) section). highi2 is set to 1 when the chan- nel 2 current exceeds its high threshold. highi2 resets to 0 after reading the flag register. lowi2 is set to 1 when the channel 2 current drops below its low threshold. lowi2 resets to 0 after reading the flag register. hight2 is set to 1 when the channel 2 temperature measurement exceeds its high threshold. hight2 resets to 0 after reading the flag register. the lowt2 is set to 1 when the channel 2 temperature measure- ment drops below its low threshold. lowt2 resets to 0 after reading the flag register. highi1 is set to 1 when the channel 1 current exceeds its high threshold. highi1 resets to 0 after reading the flag register. lowi1 is set to 1 when the channel 1 cur- rent drops below its low threshold. lowi1 resets to 0 after reading the flag register. hight1 is set to 1 when the channel 1 temperature measurement exceeds its high threshold. hight1 resets to 0 after reading the flag register. lowt1 is set to 1 when the channel 1 temperature measurement drops below its low thresh- old. lowt1 resets to 0 after reading the flag register. digital serial interface the max1385/MAX1386 contain an i 2 c-/spi-compati- ble serial interface for configuration. connect the mode- select input, sel, to dgnd to select i 2 c mode. in i 2 c mode, the max1385/MAX1386 provide address inputs a0 to a2 to allow eight devices to be connected on the same bus (see the slave address byte section). connect sel to dv dd to select spi mode. in spi mode, drive a0/ csb low to select the device. the max1385/ MAX1386 support fast (400khz) and high-speed (1.7mhz or 3.4mhz) data-transfer modes. data trans- fers occur in 8-bit bytes with acknowledge (ack) or not-acknowledge (nack) bits following each byte. the max1385/ MAX1386 are permanent slaves and do not generate their own clock signals. figure 11 shows the various read/write formats. write format use the following sequence to write a single word (see figure 11): 1) after generating a start condition (s or sr), address the max1385/MAX1386 by sending the appropriate slave address byte with its correspond- ing r/ w bit set to zero (see the slave address byte section). the max1385/MAX1386 answer with an ack bit (see the acknowledge bits section). 2) send the appropriate write command byte (see the command byte section). the max1385/MAX1386 answer with an ack bit. 3) send the most significant 8-bit section of the 16-bit data word, sending the msbs first (see the data bytes section). the max1385/MAX1386 answer with an ack bit. 4) send the least significant 8-bit section of the 16-bit data word, sending the msbs first. the max1385/ MAX1386 answer with an ack bit. 5) generate a (repeated) start or stop condition (sr or p). to write to a block of registers, use the same steps as above but repeat steps 2, 3, and 4 without any start, stop, or repeated start conditions (sr). finish the block write by generating a stop condition. read format all read operations can begin with a sr as well as an s condition. one type of read is a 5-byte operation, one is a 3-byte operation, and the other is a continuous read operation. the 5-byte operation reads from the register address contained in one of the 5 bytes sent. the 3- byte operation reads from the last register address accessed. use the following 5-byte sequence to read data bit por function d15?10 x don? care. d9?0 00 0000 0000 10-bit fine dac input code. d9 is the msb. table 22. finethrucal1 and finethrucal2 (write) data bit por function d15?8 x don? care. d7?0 0000 0000 8-bit coarse high wiper dac input code. d7 is the msb. table 20. thruhi1 and thruhi2 (read/write) data bit por function d15?8 x don? care. d7?0 0000 0000 8-bit coarse high wiper dac input code. d7 is the msb. table 21. thrulo1 and thrulo2 (read/write)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 39 16 bits of data from a max1385/MAX1386 register (see figure 11): 1) after generating a start condition (s or sr), address the max1385/MAX1386 by sending the appropriate slave address byte and its correspond- ing r/ w bit set to a 0 (see the slave address byte section). the max1385/MAX1386 then answer with an ack bit (see the acknowledge bits section). 2) send the appropriate read command byte (see the command byte section). the max1385/MAX1386 answer with an ack bit. 3) after generating a repeated start condition (sr), address the max1385/MAX1386 once more by sending the appropriate slave address byte and its r/ w bit set to 1. the max1385/MAX1386 answer with an ack bit. 4) the max1385/MAX1386 transmit the most signifi- cant 8-bit data byte of the 16-bit data word with the msb first. afterwards, the master needs to send an ack bit. 5) the max1385/MAX1386 transmit the least signifi- cant 8-bit byte of the 16-bit word with the msb first. 6) the master issues a nack bit and then generates a repeated start or stop condition (sr or p). continue to poll the current register or read multiple words (e.g., empty fifo of several conversion results) by omitting step 6 and keep issuing ack bits after each data byte. use the following 3-byte sequence to read 16 bits of data from the last accessed max1385/ MAX1386 register: 1) after generating a start condition (s or sr), address the max1385/MAX1386 by sending the appropriate 7-bit slave address byte and its corre- sponding r/ w bit set to 1 (see the slave address byte section). the max1385/MAX1386 then answer with an ack bit (see the acknowledge bits section). data bits d15 d14 d13 d12 d11 d0 conversion origin 0 0 0 0 msb lsb internal temperature sensor 0 0 0 1 msb lsb channel 1 external temperature 0 0 1 0 msb lsb channel 1 drain current (pgaout1) 0 0 1 1 msb lsb adcin1 0 1 0 0 msb lsb channel 2 external temperature 0 1 0 1 msb lsb channel 2 drain current (pgaout2) 0 1 1 0 msb lsb adcin2 0 1 1 1 reserved 1 0 0 0 reserved 1 0 0 1 reserved 1 0 1 0 reserved 1 0 1 1 reserved 1 1 0 0 reserved 1 1 0 1 reserved 1110msb lsb conversion may be corrupted. this occurs only when arriving data causes the fifo to overflow at the same time data is being read out. 1111msb bits d11?0 contain the conversion result lsb empty fifo. the current value of the flag register is provided in place of the fifo data. table 23. fifo (read) data bits por function d15?10 x don? care. d9?0 00 0000 0000 10-bit fine dac input code. d9 is the msb. table 24. rdfine1 and rdfine2 (read)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 40 ______________________________________________________________________________________ 2) the max1385/MAX1386 then transmit the contents of the last register accessed starting with the most significant 8-bit byte of the 16-bit word. msbs are sent first. afterwards, the master needs to send an ack bit. 3) the max1385/MAX1386 transmit the least signifi- cant 8-bit byte of the 16-bit word. msbs are sent first. 4) the master issues a nack bit and then generates a repeated start or stop condition (sr or p). poll the current register by omitting step 4 and continu- ing to issue ack bits after each data byte. stringing commands the max1385/MAX1386 allow commands to be strung together to minimize configuration time, which is espe- cially useful in hs mode. figure 12 shows an example of stringing a write and read command together to form a write/readback command. figure 13 shows another useful sequence for a read- modify-write application. slave address byte the max1385/MAX1386 include a 7-bit-long slave address. the first 4 bits (msbs) of the slave address are factory programmed and always 0x4h. the logic state of the address inputs (a2, a1, and a0) determine the 3 lsbs of the device address (see figure 14). connect a2, a1, and a0 to dv dd or dgnd. a maxi- mum of eight max1385/MAX1386 devices can be con- nected on the same bus at one time using these address inputs. the 8th bit of the address byte is a r/ w bit. the address byte r/ w bit is set to 0 to notify the device that a command byte will be written to the device next. the address byte r/ w bit is set to 1 to notify the device that a control byte will not be sent and to immediately send data from the last accessed register. write word format address r/ w ack write command ack data ack sr or p 7 bits 8 bits 0 data s or sr address ack sr or p 1 s or sr address ack ack data ack 0 data ack sr or p ack address ack read command ack sr address ack data ack data nack sr or p 1 0 data ack data nack 8 bits (msb) 8 bits (lsb) write block format 7 bits 8 bits r/ w write command 8 bits (msb) 8 bits (lsb) n 3-byte sequences (s, sr, and p not needed) 8 bits (msb) 8 bits (lsb) r/ w r/ w 7 bits 8 bits 7 bits 5-byte read 3-byte read r/ w 7 bits 8 bits (msb) 8 bits (lsb) s or sr s or sr figure 11. read/write formats
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 41 command byte the max1385/MAX1386 use read and write command bytes (see figure 15). the command byte consists of 8 bits and contains the address of the register. the com- mand byte also communicates to the device whether a read or write operation occurs. see the register description section for details on how to access specif- ic registers through the command byte. data bytes data bytes are clocked in/out of the device with the msb first and the lsb last (see figure 16). see the register description section for a description of data bytes for each register. bit transfer one data bit is transferred during each scl clock cycle. the data on sda must remain stable during the high period of the scl clock pulse. changes in sda while scl is high and stable are considered control signals (see the start and stop conditions section). both sda and scl remain high when the bus is not active. the interface can support fast (400khz) and high-speed (1.7mhz or 3.4mhz) data-transfer modes. start and stop conditions the master initiates a transmission with a start condi- tion (s), which is a high-to-low transition on sda while scl is high. the master terminates a transmission with a stop condition (p), which is a low-to-high transition on sda while scl is high (figure 17). a repeated start condition (sr) can be used in place of a stop condition to leave the bus active and the interface transfer speed unchanged (see the fast/high-speed modes section). bit name data bit por function x d15?d12 x don? care adcbusy d11 0 1 = adc is busy 0 = adc is not busy alubusy d10 1 1 = alu is busy 0 = alu is not busy fifoemp d9 0 1 = fifo is empty 0 = fifo is not empty fifoover d8 0 1 = fifo overflowed 0 = fifo not overflowed highi2 d7 0 1 = channel 2 high current threshold exceeded 0 = channel 2 high current threshold not exceeded lowi2 d6 0 1 = channel 2 low current threshold surpassed 0 = channel 2 low current threshold not surpassed hight2 d5 0 1 = channel 2 high temperature threshold exceeded 0 = channel 2 high temperature threshold not exceeded lowt2 d4 0 1 = channel 2 low temperature threshold surpassed 0 = channel 2 low temperature threshold not surpassed highi1 d3 0 1 = channel 1 high current threshold exceeded 0 = channel 1 high current threshold not exceeded lowi1 d2 0 1 = channel 1 low current threshold surpassed 0 = channel 1 low current threshold not surpassed hight1 d1 0 1 = channel 1 high temperature threshold exceeded 0 = channel 1 high temperature threshold not exceeded lowt1 d0 0 1 = channel 1 low temperature threshold surpassed 0 = channel 1 low temperature threshold not surpassed table 25. rdflag (read)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 42 ______________________________________________________________________________________ acknowledge bits data transfers are acknowledged with an acknowledge bit (ack) or a not-acknowledge bit (nack). both the master and the max1385/MAX1386 generate ack bits. to generate an ack, sda must be pulled low before the rising edge of the ninth clock pulse and kept low during the high period of the ninth clock pulse (see figure 20). to generate a nack, sda is pulled high before the rising edge of the ninth clock pulse and is left high for the duration of the ninth clock pulse. monitoring nack bits allow for detection of unsuccess- ful data transfers. nack bits can also be used by the master to interrupt the current data transfer to start another data transfer. the max1385/MAX1386 do not issue an ack after the last byte of a full reset write to the software clear register. fast/high-speed modes at power-up, the bus timing is set for slow-/fast-speed mode (fs mode), which allows bus speeds up to 400khz. the max1385/MAX1386 are configurable for s or sr address ack write command ack data ack sr 7 bits 0 data ack address data ack data sr or p nack ack r/ w 8 bits (msb) 8 bits (lsb) 8 bits 7 bits 1 8 bits (msb) 8 bits (lsb) r/ w figure 12. write/readback sequence s or sr address ack read command ack sr 7 bits 0 address data ack data sr or p nack ack r/ w 8 bits 7 bits 8 bits (msb) 8 bits (lsb) r/ w 1 7 bits address ack r/ w write command ack data ack data ack sr 0 8 bits 8 bits (msb) 8 bits (lsb) figure 13. read-modify-write sequence sda scl 0 10 0a2a1a0 ack 1 2 34 5 6 7 8 9 s r/ w figure 14. slave address byte
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 43 high-speed mode (hs mode), allowing bus speeds up to 3.4mhz. execute the following procedure to change from fs mode to hs mode (see figure 21). 1) generate a start condition (s). 2) send byte 00001xxx (x = don? care). the max1385/ MAX1386 issue a nack bit. 3) hs mode is entered on the 10th rising clock edge. to remain in hs mode, use repeated start conditions (sr) in place of the normal stop conditions (p) (see figure 22). all the same write and read formats sup- ported in fs mode are supported in hs mode (with the replacement of repeated start conditions for stop conditions). generating a stop condition (p) while in hs mode changes the bus speed back to fs mode. spi digital serial interface the max1385/MAX1386 feature a 4-wire spi-compati- ble serial interface capable of supporting data rates up to 16mhz. full data transfers occur in 24-bit sections. the first 8-bit byte is a command byte (c7?0). the next 16 bits are data bits (d15?0). clock signal scl may idle low or high but data is always clocked in on the rising edge of scl (cpol = cpha). write format use the following sequence to write 16 bits of data to a max1385/MAX1386 register (see figure 18): 1) pull csb low to select the device. 2) send the appropriate write command byte (see the command byte section). the command byte is clocked in on the rising edge of scl. sda scl 1 23 4 5 678 9 c6 c7 c5 c4 c3 c2 c1 c0 ack figure 15. command byte sda scl 1 2 3 4 5 6 789 d14 d15 d13 d12 d11 d10 d9 d8 ack 10 11 12 13 14 15 16 17 18 d6 d7 d5 d4 d3 d2 d1 d0 nack or ack figure 16. data bytes scl sda s sr p figure 17. start and stop conditions
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 44 ______________________________________________________________________________________ 3) send 16 bits of data (d15?0) starting with the most significant bit and ending with the least significant bit. data is clocked in on the rising edges of scl. 4) pull csb high. read format use the following sequence to read 16 bits of data from a max1385/MAX1386 register (see figure 19): 1) pull csb low to select the device. 2) send the appropriate read command byte (see the command byte section). the command byte is clocked in on the rising edges of scl. 3) receive 16 bits of data. data is clocked out on the falling edges of scl. 4) pull csb high. command byte the max1385/MAX1386 use read and write command bytes. the command byte consists of 8 bits and contains the address of the register (c7?0, see figures 18 and 19). the command byte also communicates to the device whether a read or write operation occurs. see the register description section for details on how to access specific registers through the command byte. data bytes data bytes are clocked in/out of the device with the most significant bit first and the least significant bit last (d15?0, see figures 18 and 19). see the register description section for a description of data bytes for each register. scl sda s 1 2 8 9 not acknowledge acknowledge figure 20. acknowledge bits scl c6 c5 c4 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cr/w din csb a rising edge of csb during this period completes a valid write command. figure 18. spi write format scl c6 c5 c4 c3 c2 c1 c0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cr/w din csb dout figure 19. spi read format
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 45 applications information adc clock mode 11 see figure 23 for an example of configuring a conver- sion scan for internal temperature, pgaout1, and adcin1 in clock mode 11 using the internal reference. timing symbols are referenced in the miscellaneous timing characteristics section. see figure 24 for an example of configuring a conver- sion scan for adcin1, external temperature sensor 2, and pgaout2 in clock mode 11 using the internal ref- erence. timing symbols are referenced in the miscellaneous timing characteristics section. temperature-threshold examples table 26 shows some examples of temperature settings in two?-complement form. leap-frogging the dacs for 18 bits of resolution each dac stage is configurable for leapfrog operation by using the 8-bit coarse dacs in conjunction with the 10-bit fine dac. use the following procedure for setting 18 bits of resolution: 1) write to the coarse dac1/dac2 write-through low wiper input register (thrulo1/thrulo2) 2) write to the coarse dac1/dac2 write-through high wiper input register (thruhigh1/thruhigh2) with a value one higher or one lower than written to the low wiper register. master to slave slave to master fs mode fs mode s master code a sr slave address a command/data sr slave add hs mode continues r/ w fs mode n bytes plus ack hs mode can also be continued with a command byte a p figure 22. changing to fs mode or staying in hs mode scl s 00 0 01 x xx a sr hs-mode master code sda hs mode fs mode figure 21. changing to hs mode
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 46 ______________________________________________________________________________________ 3) write to the fine dac1/dac2 write-through input register without autocalibration (finethru1/ finethru2). if the coarse dac1/dac2 low wiper is higher than the coarse dac1/dac2 high wiper, invert the fine dac1/dac input register code. the resulting output when the high wiper is higher than the low wiper is shown below: where finecode is the value written to the fine dac1/dac2 input register, and lowcode is the value v finecode v lowcode dacref dacref 22 18 8 + user writes to the analog-to-digital conversion register to set up conversion scan of adcin2, external temperature sensor2, and pgaout2 adcin2 conversion result stored in fifo external temperature sensor 2 conversion result stored in fifo pgaout2 conversion result stored in fifo end of scan, ref and temp sensor power down automatically 2.0 s acquisition for adcin1 5.5 s conversion time for adcin1 idle, but ref and temp sensor stay powered up temp conversion in ~40 s temp sensor powers up and acquires in ~6.7 s int reference powers up in ~60 s cnvst internal busy t apuint t cnv11 t acq11 5.5 s conversion time for adcin2 2 s acquisition of adcin2 idle, but ref stays powered up figure 24. adc clock mode 11, example 2 cnvst user writes to the analog-to-digital conversion register to set up conversion scan of internal temperature, pgaout1, and adcin1 internal busy int reference powers up in ~60 s temp sensor powers up and acquires in ~6.7 s temp conversion in ~40 s idle, but ref and temp sensor stay powered up idle, but ref and temp sensor stay powered up 47 s acquisition for pgaout1 5.5 s conversion time for pgaout1 2 s acquisition for adcin1 5.5 s conversion time for adcin1 end of scan, ref and temp sensor power down automatically t acq11 t acq11 internal temperature conversion result is stored in fifo pgaout1 conversion result stored in fifo adcin1 conversion result stored in fifo t cnv11 figure 23. adc clock mode 11, example 1
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 47 written to the coarse dac1/dac2 input low wiper reg- ister. the resulting output when the low wiper is higher than the high wiper is: basic software initialization the max1385/MAX1386 do not power on all internal blocks when full power is first applied. software must write to register 0x64 twice with bit d7 set to 0 during initialization to enable full operation. a basic initializa- tion sequence is shown in table 27. regulating vgs vs. temperature the max1385/MAX1386 can be used along with a microcontroller to perform closed-loop regulation of the ldmos fet bias current. for example, software can read the temperature and use a calibrated look-up table to determine a new value for the gate drive. as an example, in noncontinuous conversion mode, read temperature from remote diode 1 by writing to the adccon register (0x62) with bit d1 set to 1. wait for busy to go high and then low. read the adc result from the fifo (0x80). the result bits d15?12 = 0001 indicate the measurement source is the external tem- perature sensor dxp1/dxn1, and bits d11?3 indicate two?-complement temperature in degrees celsius. bits d2, d1, and d0 are temperature sublsbs. gate voltage drive range must be previously deter- mined during initialization by setting the coarse dac1 high and low limits. write a new value to finethru1 to immediately change the output gate1 between the high and low wiper limits based on the previous tem- perature measurement. the regulation software may also use the alarm thresh- old limits to determine whether temperature and current ? + v finecode v lowcode dacref dacref 22 18 8 command byte data word description 0x64 0x0008 bring the device out of shutdown mode. 0x64 0x0008 set internal reference and both dac channels on. 0x20 0x02a8 set the channel 1 high-temperature threshold to +85?. 0x22 0x0ec0 set the channel 1 low-temperature threshold to -40?. 0x24 0x02c1 set the channel 1 high-current threshold to 4.3a for 50m ? r sense , av pga = 2, and v refadc = 2.5v. 0x26 0x0106 set the channel 1 low-current threshold to 1.6a for 50m ? r sense , av pga = 2, and v refadc = 2.5v. 0x28 0x02a8 set the channel 2 high-temperature threshold to +85?. 0x2a 0x0ec0 set the channel 2 low-temperature threshold to -40?. 0x2c 0x02c1 set the channel 2 high-current threshold to 4.3a for 50m ? r sense , av pga = 2, and v refadc = 2.5v. 0x2e 0x0106 set the channel 2 low-current threshold to 1.6a for 50m ? r sense , av pga = 2, and v refadc = 2.5v. 0x30 0x000f set av pga1 and av pga2 to 2, clock mode to 00 and adc/dac references to internal. 0x32 0x0000 set alarm, safe1, and safe2 to depend on nothing (por). 0x60 0x0000 set alarm, safe1, and safe2 for push-pull/active-high (por). 0x74 0x00cc set coarse dac1 high wiper to 204. 0x76 0x0066 set coarse dac1 low wiper to 102 (v gate = 1.99v for max1385, v gate = 3.98v for MAX1386). 0x7a 0x00cc set coarse dac2 high wiper to 204. 0x7c 0x0066 set coarse dac2 low wiper to 102 (v gate = 1.99v for max1385, v gate = 3.98v for MAX1386). 0x52 0x01ff set fine dac1 to midscale. 0x56 0x01ff set fine dac2 to midscale. table 27. basic software initialization temperature setting two? complement -40? 1110 1100 0000 -1.625? 1111 1111 0011 0? 0000 0000 0000 +27.125? 0000 1101 1001 +105? 0011 0100 1000 table 26. temperature-threshold settings examples
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 48 ______________________________________________________________________________________ limits are within the safe operating area. configure the adc for continuous conversions to allow continuous measurement and testing against configured alarm thresholds. connect safe_ to opsafe_ to immediately force the gate drive to gategnd in the event of an alarm-related condition (current or temperature). triggering dac calibration performing the autocalibration routines requires use of the internal adc, the internal alu, and can also increase the power dissipation of the part. tables 28 and 29 detail which commands trigger autocalibration and which commands do not. action required recommended command sequence other possible command sequences update fine dac_ without triggering autocalibration. write to fine_. write to ldac to update fine dac_. write to finethru_ to immediately update fine dac_. update high wiper coarse dac_ without triggering autocalibration. write to hiwipe_ with hcal set to 0. write to ldac to update high wiper coarse dac_. write to thruhi_ to immediately update high wiper coarse dac_. update low wiper coarse dac_ without triggering autocalibration. write to lowipe_ with lcal set to 0. write to ldac to update low wiper coarse dac_. write to thrulo_ to immediately update low wiper coarse dac_. immediately update fine dac_ without triggering autocalibration. write to finethru_. none. immediately update high wiper coarse dac_ without triggering autocalibration. write to thruhi_. none. immediately update low wiper coarse dac_ without triggering autocalibration. write to thrulo_. none. update the high, low, and fine components of dac_ simultaneously without triggering autocalibration. write to hiwipe_, lowipe, and fine_. write to ldac to update dac_. none. table 28. dac write commands without autocalibration 0000 0000 0000 0000 0000 0001 0000 0000 0010 input voltage (lsb) 1111 1111 1100 1111 1111 1110 1111 1111 1111 1111 1111 1101 full-scale transition binary output code 4093 4095 0 1 2 3 0000 0000 0011 v refadc v refadc 1 lsb = v refadc 4096 1000 0000 0000 1000 0000 0001 1000 0000 0010 -256 c temperature ( c) 0000 0000 0001 0111 1111 1110 0111 1111 1111 1111 1111 1111 0000 0000 0000 0111 1111 1101 1 lsb = +0.125 c output code 0 c +255.875 c figure 25. adc transfer function figure 26. temperature transfer function
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 49 action required recommended command sequence other possible command sequences update fine dac_ and trigger autocalibration. write to finecal_. autocalibration begins after writing to finecal_. write to ldac to update fine dac_. write to finecalthru_ to immediately update fine dac_. update high wiper coarse dac_ and trigger autocalibration. write to hiwipe_ with hcal set to 1. autocalibration begins after writing to ldac and high wiper coarse dac_ is updated thereafter. none. update low wiper coarse dac_ and trigger autocalibration. write to lowipe_ with lcal set to 1. autocalibration begins after writing to ldac and low wiper coarse dac_ is updated thereafter. none. immediately update fine dac_ and trigger autocalibration. write to finecalthru_. none. immediately update high wiper coarse dac_ and trigger autocalibration. this action is not possible. see the recommended sequence above ?pdate high wiper coarse dac_ and trigger autocalibration. none. immediately update low wiper coarse dac_ and trigger autocalibration. this action is not possible. see the recommended sequence ?pdate low wiper coarse dac_ and trigger autocalibration. none. update the high, low, and fine components of dac_. write to hiwipe_ with hcal set to 1. write lowipe_ with lcal set to 1. write to ldac to update high and low wipers with autocalibrated values. write to finecalthru_ to trigger fine dac_ autocalibration and update dac_. hiwipe_ and lowipe_ can be written to in any order but must be followed by ldac and then a fine dac_ write (to finecalthru_ or finecal_ with another ldac). this ensures that the fine dac_ autocalibration is run after the coarse dac_ autocalibration. table 29. dac write commands with autocalibration
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface 50 ______________________________________________________________________________________ scl scl sda sda/din alarm safe1 safe2 dxp1 dxn1 dxp2 dxn2 *select r f and c f based on desired filter cut-off frequency. limit r f to minimize offset errors. gate1 gate2 a0/csb a1/dout a2/n.c. opsafe1 opsafe2 busy adcin1 adcin2 dgnd cnvst (at ldmosfet) (at ldmosfet) +5v dv dd gatev dd av dd refdac refadc cs1+ cs1- cs2+ cs2- gategnd agnd pgaout2 pgaout1 rf input drain supply rf output c f * r f * rf output rf input drain supply external reference 5v 5v microcontroller 5v max1385 MAX1386 sel r f * c f * typical operating circuit (i 2 c mode)
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface ______________________________________________________________________________________ 51 n.c. n.c. cs1+ cs1- cs2- n.c. cs2+ n.c. opsafe2 gate1 gate2 opsafe1 a0/csb cnvst sel alarm safe2 n.c. refdac dxn1 refadc dxp1 safe1 dgnd pgaout2 av dd n.c. agnd gatev dd gategnd agnd adcin2 adcin1 dxn2 dxp2 busy n.c. a1/dout sda/din scl n.c. a2/n.c. pgaout1 n.c. n.c. n.c. dv dd max1385 MAX1386 agnd top view *exposed pad *exposed pad internally connected to agnd 1 2 34 56 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 37 38 39 40 41 42 43 44 45 46 47 48 24 23 22 21 20 19 18 17 16 15 14 13 tqfn + pin configuration package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 48 tqfn-ep t4877-6 21-0044
max1385/MAX1386 dual rf ldmos bias controllers with i 2 c/spi interface maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 52 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. appendix: recommended power-up code sequence the following section shows the recommended startup code for the max1385. this code ensures clean startup of the part, irrespective of power-supply ramp speed and starts the device regulating to 312.5mv on both channels. change the thrudac writes to change the voltage across the sense resistor. note it should be run after the power supplies have stabilized. *double reset. this ensures that the internal rom is reset correctly after power-up and that the rom data is latched correctly irre- spective of power-supply ramp speed. register mnemonic register address (hex) code written notes shut 0x64 0x0080 removes the global power. shut 0x64 0x0080 powers up all parts of the max1385 and forces the internal reference to remain powered. the internal oscillator is required for the subsequent reset command. sclr 0x68 0x0100 arms the full reset. sclr 0x68 0x0200 completes the full reset. sclr 0x68 0x0100 arms the full reset.* sclr 0x68 0x0200 completes the full reset.* shut 0x64 0x0080 removes the global power. shut 0x64 0x0080 powers up all parts of the max1385 and forces the internal reference to remain powered. the internal oscillator is required for the subsequent reset command. dcfig 0x30 0x000a selects internal references for both dac and adc. pgacal 0x4e 0x0002 runs autocalibration on both pga channels to set the input referred offset to < 50?. busy goes low after approximately 30ms and then the v gate dacs can be set.

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